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PSD33XX (TURBO SERIES)
Fast 8032 MCU With Programmable Logic
PRELIMINARY DATA
FEATURES SUMMARY 8-bit System On Chip for Embedded Control The Turbo PSD3300 Series combines a powerful, 8051-based microcontroller with a unique memory structure, programmable logic, and a rich peripheral mix to form the ideal SOC for embedded control. At it's core is a fast, 4-cycle 8032 MCU with a 6-byte instruction prefetch queue and a 4entry, fully associative branching cache to maximize MCU performance, enabling smaller loops of code to execute very quickly. Code development is easily managed without a hardware In-Circuit Emulator by using the serial JTAG debug interface. JTAG is also used for InSystem Programming (ISP), perfect for manufacturing and lab development. The 8032 core is coupled to Programmable System Device (PSD) architecture to optimize 8032 memory structure, offering two independent banks of Flash memory that can be placed at virtually any address within 8032 program or data space, and easily paged beyond 64K bytes using on-chip programmable decode logic. Dual Flash memory banks provide a robust solution for remote product updates in the field through In-Application Programming (IAP). Dual Flash banks also support EEPROM emulation, eliminating the need for external EEPROM chips. A wide variety of Flash and SRAM memory sizes are available, some reaching the largest on the 8bit MCU market today. General purpose programmable logic is included to build an endless variety of glue-logic, saving external chips. This SOC also provides a rich array of peripherals, including analog and supervisor functions. s Fast Turbo 8032 MCU - Advanced 8032 core: four clocks per instruction instruction pre-fetch; branching cache - 10 MIPs peak performance @40MHz clock 5.0V VCC ... 8 MIPs peak @40MHz, 3.3V VCC - 8032 core compatible with 3rd party tools - Internal clock divider for low-power mode - Three 8032 16-bit timers and external interrupts - Dual XDATA pointers with auto incr & decr
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Programmable Counter Array (PCA) - Dual independent timer/counter blocks, each with three 16-bit timer/counters modules - Use any of the 6 modules as: 16-bit capture/ compare, 16-bit timer/counter, 8/16 bit PWM. JTAG Debug and In-System Programming - Set Breakpoints, trace, single-step, display, modify memory, and SFRs; external event pin. - ISP the chip in 10-20sec, 8032 not involved. Programmable Logic, General Purpose - 16 Macrocells with architecture similar to industry standard 22V10 PLDs - Create shifters, state machines, chip-selects, glue-logic to keypads, panels, LCDs, others - Configure PLD with simple PSDsoft Express software ... download at no charge from web. Dual Flash Memories w/Memory Managment - True READ-while-WRITE concurrent access - Main Flash size: 64K, 128K, or 256K Bytes - Secondary Flash size: 16K or 32K bytes - 100,000 min erase cycles, 15 year retention - On-chip programmable memory decode logic SRAM - 2K, 8K, or 32K Bytes; use as XDATA or code. - Capable of battery backup w/external battery. Peripheral Interfaces - (8) 10-bit ADC channels, 8 usec conversion time - I2C Master/Slave bus controller up to 800kHz - SPI Master bus controller, up to 10Mhz - Two standard UARTs with independent baud - IrDA protocol support up to 115K baud rate - 8032 address/data bus (80 pin package only) - Up to 46 I/O; eight can sink/source 10mA. Supervisor Functions - Watchdog timer, VCC monitor with 10ms Reset generator, Filtered Reset input
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July 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Rev. 1.0
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Operating Range - 3.3V applications: VCC = 3.3V 10% - 5.0V applications: VCC: Both 5.0V 10% and 3.3V 10% sources are required. - Temp: -40C to +85C (Industrial Range)
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TQFP Packaging - 52-pin (10x10mm) or 80-pin (12x12mm)
Figure 1. 52-lead, Thin, Quad, Flat Package
Figure 2. 80-lead, Thin, Quad, Flat Package
TQFP52 (T)
TQFP80 (U)
Table 1. PSD33XX Device Selector Guide
Main Flash Kbyte 2nd Flash Kbyte 3 std I2 C timers, ADC, 8032 JTAG, SPI, +6 prog GPIO Bus ISP, & Dual Super- timer/ Pins Debug UART, visor PWM IrDA modules Yes Yes Yes Up to 37 Up to 37 Up to 37 Up to 37 Up to 46 Up to 46 Up to 37 Up to 37 Up to 46 Up to 46 No yes
Part No.
SRAM Kbyte
PLD
Pkg
Op VCC
PSD 3312DV40T6 PSD 3312D40T6 PSD 3333DV40T6 PSD 3333D40T6 PSD 3334DV40T6 16 PSD 3334D40U6 PSD 3354DV40T6 PSD 3354D40T6 PSD 3354DV40T6 16 PSD 3354D40U6
64K
16K
2K
16 macro cells 16 macro cells 16 macro cells 16 macro cells 16 macro cells 16 macro cells 16 macro cells 16 macro cells 16 macro cells 16 macro cells
52-pin 3.3V10% TQFP 52-pin 3.3V & TQFP 5.0V10% 52-pin 3.3V10% TQFP 52-pin 3.3V & TQFP 5.0V10% 80-pin 3.3V10% TQFP 80-pin 3.3V & TQFP 5.0V10% 52-pin 3.3V10% TQFP 52-pin 3.3V & TQFP 5.0V10% 80-pin 3.3V10% TQFP 80-pin 3.3V & TQFP 5.0V10%
64K
16K
2K
Yes
Yes
Yes
No
Yes
128K
32K
8K
Yes
Yes
Yes
No
Yes
128K
32K
8K
Yes
Yes
Yes
No
Yes
256K
32K
8K
Yes
Yes
Yes
Yes
Yes
256K
32K
8K
Yes
Yes
Yes
Yes
Yes
256K
32K
32K
Yes
Yes
Yes
No
Yes
256K
32K
32K
Yes
Yes
Yes
No
Yes
256K
32K
32K
Yes
Yes
Yes
Yes
Yes
256K
32K
32K
Yes
Yes
Yes
Yes
Yes
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TABLE OF CONTENTS PSD33XX HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8032 CORE PERFORMANCE ENHANCEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Instruction Pre-fetch Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Branch Cache (BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MCU MODULE DISCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Special Function Registers (SFRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Dual Data Pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data Pointer Control Register, DPTC (85H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data Pointer Mode Register, DPTM (86H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Debug Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 External Int0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Timer 0 and 1 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Timer 2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I2C Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 External Int1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PCA Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 UART Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Debug Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Interrupt Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Interrupts Enable Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 POWER SAVINGS MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Idle Mode Function Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 REDUCED FREQUENCY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CPU CLOCK CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I/O PORTS (MCU MODULE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Port 1 Register P1SFS0, Port 1 Register P1SFS1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Port 3 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Port 4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Port 4 High Current Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MCU MEMORY BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 READ Bus Cycle (Code or XDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 WRITE Bus Cycle (XDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bus Control Register (BUSCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SUPERVISORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Low VCC Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Watchdog Timer Overflow Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Debug Unit Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power-up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Watchdog Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TIMER/COUNTERS (TIMER0, TIMER1, AND TIMER 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Timer 0 and Timer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STANDARD SERIAL INTERFACE (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Serial Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 IRDA INTERFACE TO INFRARED TRANSCEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Baud Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 I2C Registers Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Serial Status Register (S1STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Data Shift Register (S1DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Address Register (S1ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SPI (SYNCHRONOUS PERIPHERAL INTERFACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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PSD33XX
Slave Select Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Port 1 ADC Channel Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PROGRAMMABLE COUNTER ARRAY (PCA) WITH PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 PCA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Operation of TCM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Toggle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PWM Mode - (X8), Fixed Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PWM Mode - (X8), Programmable Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PWM Mode - Fixed Frequency, 16-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Writing to Capture/Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Control Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 TCM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PSD MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . 67 PSD MODULE DETAILED OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 MEMORY BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 68 Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Flash Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 READ Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 The Turbo Bit in PSD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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I/O PORTS (PSD MODULE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Ports A and B - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Port C - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Port D - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Reset of Flash Memory Erase and Program Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 95 Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Security and Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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Figure 3. TQFP52 Connections
41 P1.7/SPISEL_(2)/ADC7 40 P1.6/SPITXD(2)/ADC6
47 3.3V VCC/VREF(3)
42 PB7P1.6/ADC2
44 RESET_IN_
45 GND
52 PB0
51 PB1
50 PB2
49 PB3
48 PB4
46 PB5
43 PB6
PD1/CLKIN 1 PC7 2 JTAG TDO 3 JTAG TDI 4 DEBUG 5 3.3V VCC 6 PC4/TERR_ 7 VDD(1) 8 GND 9 PC3/TSTAT 10 PC2/VSTBY 11 JTAG TCK 12 JTAG TMS 13
39 P1.5/SPIRXD(2)/ADC5 38 P1.4/SPICLK(2)/ADC4 37 P1.3/TXD1(IrDA)(2)/ADC3 36 P1.2/RXD1(IrDA)(2)/ADC2 35 P1.1/T2X(2)/ADC1 34 P1.0/T2(2)/ADC0 33 VDD(1) 32 XTAL2 31 XTAL1 30 P3.7/I2CSCL 29 P3.6/I2CSDA 28 P3.5/C1 27 P3.4/C0
SPISEL_(2)/PCACLK1/P4.7 14
SPITXD(2)/TCM5/P4.6 15
SPIRXD(2)/TCM4/P4.5 16
17
18
GND 19
20
T2X(2)/TCM1/P4.1 21
T2(2)/TCM0/P4.0 22
RXD0/P3.0 23
TXD0/P3.1 24
EXTINT0/TG0/P3.2 25
TXD1(IrDA)(2)/PCACLK0/P4.3
SPICLK(2)/TCM3/P4.4
RXD1(IrDA)(2)/TCM2/P4.2
EXTINT1/TG1/P3.3 26
AI07822
Note: 1. For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1. 3. VREF and 3.3V VCC are shared in the 52-pin package only. ADC channels must use 3.3V as VREF for the 52-pin package.
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Figure 4. TQFP80 Connections
64 P1.7/SPISEL_(2)/ADC7 61 P1.6/SPITXD(2)/ADC6 79 P3.2/EXINT0/TG0
68 RESET_IN_
75 P3.0/RXD0
77 P3.1/TXD0
72 3.3V VCC 71 PB5
63 PSEN_
70 VREF
62 WR_
69 GND
65 RD_
80 PB0
78 PB1
76 PB2
74 PB3
73 PB4
67 PB6
66 PB7
PD2 1 P3.3/TG1/EXINT1 2 PD1 3 ALE 4 PC7 5 JTAG TDO 6 JTAG TDI 7 DEBUG 8 PC4/TERR_ 9 3.3V VCC 10 NC 11 VDD(1) 12 GND 13 PC3/TSTAT 14 PC2/VSTBY 15 JTAG TCK 16 NC 17 SPISEL_(2)/PCACLK1/P4.7 18 SPITXD(2)/TCM5/P4.6 19 JTAG TMS 20
60 P1.5/SPIRXD(2)/ADC5 59 P1.4/SPICLK(2)/ADC4 58 P1.3/TXD1(IrDA)(2)/ADC3 57 MCU A11 56 P1.2/RXD1(IrDA)(2)/ADC2 55 MCU A10 54 P1.1/T2X(2)/ADC1 53 MCU A9 52 P1.0/T2(2)/ADC0 51 MCU A8 50 VDD(1) 49 XTAL2 48 XTAL1 47 MCU AD7 46 P3.7/I2CSCL 45 MCU AD6 44 P3.6/I2CSDA 43 MCU AD5 42 P3.5/C1 41 MCU AD4
PA7 21
PA6 22
SPIRXD(2)/TCM4/P4.5 23
PA5 24
SPICLK(2)/TCM3/P4.4 25
PA4 26
TXD1(IrDA)(2)/PCACLK0/P4.3 27
PA3 28
GND 29
RXD1(IrDA)(2)/TCM2/P4.2 30
T2X(2)/TCM1/P4.1 31
PA2 32
T2(2)/TCM0/P4.0 33
PA1 34
PA0 35
MCU AD0 36
MCU AD1 37
MCU AD2 38
MCU AD3 39
P3.4/C0 40
AI07823
Note: NC = Not Connected 1. For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1.
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Table 2. Pin Descriptions
Port Pin Signal Name 80Pin No. 36 52-Pin In/Out No.(1) Function Basic External Bus Multiplexed Address/Data bus A0/D0 Multiplexed Address/Data bus A1/D1 Multiplexed Address/Data bus A2/D2 Multiplexed Address/Data bus A3/D3 Multiplexed Address/Data bus A4/D4 Multiplexed Address/Data bus A5/D5 Multiplexed Address/Data bus A6/D6 Multiplexed Address/Data bus A7/D7 External Bus, Addr A8 External Bus, Addr A9 External Bus, Addr A10 External Bus, Addr A11 General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin Timer 2 Count input (T2) Timer 2 Trigger input (T2X) UART1 or IrDA Receive (RxD1) UART or IrDA Transmit (TxD1) SPI Clock Out (SPICLK) SPI Receive (SPIRxD) SPI Transmit (SPITxD) SPI Slave Select (SPISEL) UART0 Receive (RxD0) ADC Channel 0 input (ADC0) ADC Channel 1 input (ADC1) ADC Channel input (ADC2) ADC Channel input (ADC3) ADC Channel input (ADC4) ADC Channel input (ADC5) ADC Channel input (ADC6) ADC Channel input (ADC7) 2 3 4 5 6 7 Alternate 1 Alternate 2
MCUAD0
AD0
N/A
I/O
MCUAD1
AD1
37
N/A
I/O
MCUAD2
AD2
38
N/A
I/O
MCUAD3
AD3
39
N/A
I/O
MCUAD4
AD4
41
N/A
I/O
MCUAD5
AD5
43
N/A
I/O
MCUAD6
AD6
45
N/A
I/O
MCUAD7 MCUA8 MCUA9 MCUA10 MCUA11 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0
AD7 A8 A9 A10 A11 T2 ADC0 T2EX ADC1 RxD1 ADC2 TXD1 ADC3 SPICLK ADC4 SPIRxD ADC6 SPITXD ADC6 SPISEL ADC7 RxD0
47 51 53 55 57 52 54 56 58 59 60 61 64 75
N/A N/A N/A N/A N/A 34 35 36 37 38 39 40 41 23
I/O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O
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Signal Name TXD0 EXINT0 TGO INT1 C0 C1 I2CSDA I2CSCL T2 TCM0 T2X TCM1 RXD1 TCM2 TXD1 PCACLK0 SPICLK TCM3 SPIRXD TCM4 SPITXD SPISEL PACCLK1 80Pin No. 77 79 52-Pin In/Out No.(1) 24 25 I/O I/O Function Basic General I/O port pin General I/O port pin Alternate 1 UART0 Transmit (TxD0) Interrupt 0 input (EXTINT0)/Timer 0 gate control (TG0) Interrupt 1 input (EXTINT1)/Timer 1 gate control (TG1) Counter 0 input (C0) Counter 1 input (C1) I2C Bus serial data (I2CSDA) I2C Bus clock (I2CSCL) Program Counter Array0 PCA0-TCM0 PCA0-TCM1 PCACLK0 PCACLK0 Program Counter Array1 PCA1-TCM3 PCA1-TCM4 PCA1-TCM5 PCACLK1 Alternate 2
Port Pin P3.1 P3.2
P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 VREF RD_ WR_ PSEN_ ALE RESET_ IN_ XTAL1 XTAL2 DEBUG
2 40 42 44 46 33 31 30 27 25 23 19 18 70 65 62 63 4 68 48 49 8
26 27 28 29 30 22 21 20 18 17 16 15 14 N/A N/A N/A N/A N/A 44 31 32 5
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O O O O I I O I/O
General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin Reference Voltage input for ADC READ Signal, external bus WRITE Signal, external bus PSEN Signal, external bus Address Latch signal, external bus Active low reset input Oscillator input pin for system clock Oscillator output pin for system clock I/O to the MCU Debug Unit
Timer 2 Count input (T2) Timer 2 Trigger input (T2X) UART1 or IrDA Receive (RxD1) UART1 or IrDA Transmit (TxD1) SPI Clock Out (SPICLK) SPI Receive (SPIRxD) SPI Transmit (SPITxD) SPI Slave Select (SPISEL)
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Signal Name 80Pin No. 35 34 32 28 26 24 22 21 80 78 76 74 73 71 67 66 20 16 15 14 9 7 6 5 CLKIN 3 52-Pin In/Out No.(1) N/A N/A N/A N/A N/A N/A N/A N/A 52 51 50 49 48 46 43 42 13 12 11 10 7 4 3 2 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I O I/O I/O Function Basic General I/O port pin General I/O General I/O General I/O General I/O General I/O General I/O General I/O General I/O General I/O General I/O General I/O General I/O General I/O port pin port pin port pin port pin port pin port pin port pin port pin port pin port pin port pin port pin port pin Alternate 1 Alternate 2 All Port A pins support: 1. PLD Macro-cell outputs, or 2. PLD inputs, or 3. Latched Address Out (A0-A7), or 4. Peripheral I/O Mode
Port Pin PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 JTAGTMS JTAGTCK PC2 PC3 PC4 JTAGTDI JTAGTDO PC7 PD1
TMS TCK VSTBY TSTAT TERR TDI TDO
General I/O port pin General I/O port pin JTAG pin (TMS) JTAG pin (TCK) General I/O port pin General I/O port pin General I/O port pin JTAG pin (TDI) JTAG pin (TDO) General I/O port pin General I/O port pin SRAM Standby voltage input (VSTBY) Optional JTAG Status (TSAT) Optional JTAG Status (TERR)
All Port B pins support: 1. PLD Macro-cell outputs, or 2. PLD inputs, or 3. Latched Address Out (A0-A7)
PLD Macrocell output, or PLD input PLD, Macrocell output, or PLD input PLD, Macrocell output, or PLD input
PLD, Macrocell output, or PLD input 1. PLD I/O 2. Clock input to PLD and APD 1. PLD I/O 2. Chip select ot PSD Module
PD2 3.3V-VCC 3.3V-VCC VDD 3.3V or 5V VDD 3.3V or 5V GND GND GND NC NC
CSI
1 10 72 12
N/A 6 47 8
I/O
General I/O port pin VCC - MCU Module VCC - MCU Module VDD - PSD Module VDD - 3.3V for 3V VDD - 5V for 5V VDD - PSD Module VDD - 3.3V for 3V VDD - 5V for 5V
50 13 29 69 11 17
33 9 19 45 N/A N/A
Note: 1. N/A = Signal Not Available on 52-pin package.
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PSD33XX HARDWARE DESCRIPTION The PSD33XX has a modular architecture with two main functional modules: the MCU Module and the PSD Module (see Figure 5). The MCU Module consists of a fast 4-cycle 8032 core, peripherals, and other system-supporting functions. The PSD Module provides configurable Program and Data memories to the 8032 CPU core. In addition, it has its own set of I/O ports and a PLD with 16 macrocells for general logic implementation. Ports A,B,C, and D are general purpose programmable I/O ports that have a port architecture which is different from I/O Ports in the MCU Module. Figure 5. PSD33XX Functional Modules
Port 3 - UART0, Intr, Timers Port 1 - T imer, ADC, SPI Port 4 - PCA, PWM, UART1 Port 3 I2C
The PSD Module communicates with the MCU Module through the internal address, data bus (A0-A15, D0-D7) and control signals (RD_, WR_, PSEN_, ALE, RESET_). The user defines the Decoding PLD in the PSDsoft Development Tool and can map the resources in the PSD Module to any program or data address space. The modules have their own separate power supply pins. The MCU module runs at 3.3V while the PSD module can be 3.3V or 5V, depending on the device. The MCU module can interface to a 5V PSD module as its I/O ports are 5V tolerant.
MCU Module
Port 3 Port 1 T urbo 8032 Core Dual UARTs Interrupt 3T imer / Counters 256 Byte SRAM
XT AL Clock Unit
10-bit ADC
SPI
PCA PWM Counters
I2 C Unit
VCC Pins 3.3V
Dedicated Memory Interface Prefetch, Jump Cache 8-Bit Die to Die Bus Enhanced MCU Interface
PSD Page Register
8032 Internal Bus
Ext. Bus Reset Input
LVD
JT AG DEBUG
Internal Reset
Reset Logic
WDT
Reset Pin
Main Flash
Decode PLD
Secondary Flash
PSD Reset SRAM
PSD Module
PSD Internal Bus
JT ISP AG
CPLD - 16 MACROCELLS
VDD Pins 3.3V or 5V
uPSD33XX
Port C JTAG and GPIO
Port A,B,C PLD I/O and GPIO
Port D GPIO
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MEMORY ORGANIZATION The PSD33XX Devices' fast 8032 Core has separate 64KB address spaces (see Figure 6) for Program memory and Data Memory. Program memory is where the 8032 executes instructions from. Data memory is used to hold data variables. Flash memory can be mapped in either program or data space. The Flash memory consists of two flash memory blocks: the main Flash and the Secondary Flash. Except during flash memory programming or update, Flash memory can only be read, not written to. A Page Register is used to access memory beyond the 64K bytes address space. Refer to the PSD Module for details on mapping of the Flash memory. The 8032 core has two types of data memory (internal and external) that can be read and written. The internal SRAM consists of 256 bytes, and includes the stack area. The Special Function Registers (SFRs) occupy the upper 128 bytes of the internal SRAM, the registers can be accessed by Direct addressing only. There is a block of external SRAM in the PSD33XX which resides in the PSD Module that can be mapped to any address space defined by the user.
Program Memory The program memory consists of two Flash memory: Main Flash (64K, 128K, or 256K Bytes) and Secondary Flash (16K, 32K Bytes). The Flash memory can be mapped to any address space as defined by the user in the PSDsoft Tool. It can also be mapped to Data memory space during Flash memory update or programming. After reset, the CPU begins execution from location 0000h. Each interrupt is assigned a fixed location in Program Memory. The interrupt causes the CPU to jump to that location, where it commences execution of the service routine. External Interrupt 0, for example, is assigned to location 0003h. If External Interrupt 0 is going to be used, its service routine must begin at location 0003h. If the interrupt is not going to be used, its service location is available as general purpose Program Memory. The interrupt service locations are spaced at 8byte intervals: 0003h for External Interrupt 0, 000Bh for Timer 0, 0013h for External Interrupt 1, 001Bh for Timer 1 and so forth. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use.
Figure 6. PSD33XX Memory Map and Address Space
Main Flash
Ext. RAM
Secondary Flash
64KB, 128KB, or 256KB
Int. RAM FF Indirect Addressing 7F
SFR Direct Addressing 2KB, 8KB, or 32KB
16KB or 32KB
0
Indirect or Direct Addressing
Flash Memory Space
Internal RAM Space 256 bytes
External RAM Space
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Data Memory The internal data memory is divided into four physically separated blocks: 256 bytes of internal RAM, 128 bytes of Special Function Registers (SFRs), and XRAM-PSD in the PSD Module. RAM Four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. The stack depth is only limited by the available internal RAM space of 256 bytes. XRAM-PSD The XRAM-PSD (2KB, 8KB, or 32KB) reside in the PSD Module and can be mapped to any address space through the DPLD (Decoding PLD) as defined by the user in PSDsoft Development tool. The XRAMPSD has a battery back-up feature that allows the data to be retained in the event of a power outage. The battery is connected to the Port C PC2 pin. This pin must be configured in PSDSoft to be battery back-up.
8032 CORE PERFORMANCE ENHANCEMENTS The PSD33XX's CPU Core has implemented an Instruction Pre-fetch Queue (PFQ) and a Branch Cache (BC) to provide continuous code stream to the execution unit. The codes are fetched from PSD Module flash memory to be stored in the PFQ and Branch Cache. Instruction Pre-fetch Queue The PFQ logic will fetch 8-bit data from the memories in the PSD Module. The logic will queue up to 6 bytes from the program instruction stream and will "feed" the requested bytes to the CPU core as the instructions are executed. The Pre-fetch Queue will make use of free memory bandwidth and try to keep the Pre-fetch Queue full with the next sequence of instructions. When a jump takes place (non sequential code access) the Pre-fetch Queue is cleared and will need to start over at from the new address. The Pre-fetch Queue must be able to "feed" instruction bytes to the CPU core so that it does not stall when the corresponding byte is in the queue. If the requested byte is not in the
queue, then the CPU core will stall until the requested byte is read and given to the CPU and placed into the Pre-fetch Queue. Branch Cache (BC) This is a 4-word cache that maintains the destination instructions (six bytes) from the previous 4 jumps. When the CPU takes a jump or interrupt that causes a non-sequential code access, the Branch Cache is checked to see if it has a match (address being jumped to). If the cache has a hit (match) then the corresponding word of data is transferred to the Pre-fetch Queue. At the same time the instruction bytes at the target address is supplied to the CPU. The Branch Cache must be able to supply the destination instruction to the CPU in time so that the CPU does not stall when there is a cache hit to an even or odd address. If there is a cache miss, then the CPU will stall until the destination words are fetched and placed into the Branch Cache. The Branch Cache will use LRU algorithm to replace cache entries.
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MCU MODULE DISCRIPTION This section provides a detail description of the MCU Module system functions and Peripherals, including: - Special Function Registers - Debug Unit - Interrupts - Power Saving Modes - Oscillator and MCU Clock Generation - I/O Ports Special Function Registers (SFRs) A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 3. The SFRs can only be addressed directly in the address range from 80h to FFh. Sixteen address in the SFR space are both: byte- and bit-addressable. The bit-addressable SFRs are those Table 3. SFR Memory Map
F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 *ACC *SCON1 *PSW *T2CON *P4 *IP *P3 *IE *P2 *SCON0 *P1 *TCON *P0 SBUF0 P3SFS TMOD SP P4SFS0 TL0 DPL P4SFS1 TL1 DPH ADC0S TH0 CAPCOM H1 TCM MODE0 CAPCOM L3 SBUF1 SPICLKD RCAP2L CAPCOM H3 PCACL1 CAPCOM L2 TCM MODE1 PCACL0 S1SETUP SPISTAT RCAP2H CAPCOM L4 PCACH1 CAPCOM H2 TCM MODE2 PCACH0 S1CON SPITDR TL2 CAPCOM H4 PCACON1 PWMF0 CAPCOM L0 PCACON0 CAPCOM H0 PCASTA BUSCON ADAT0 TH1 DPTC WDKEY WDRST DIR ADAT1 P1SFS0 PDTM S1STA SPIRDR TH2 CAPCOM L5 TCM MODE3 UDT1 S1DAT SPICON0 IRDACON CAPCOM H5 TCM MODE4 UDT0 S1ADR SPICON1 DSTAT PWMF1 TCM MODE5 IPA CAPCOM L1 IEA DVR ACON P1SFS1 PCON *B CCON0 CCON2 CCON3 FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87
- - - - - - - - -
MCU Bus Interface Supervisory Function (LVD and Watchdog) Timers/Counter UART IrDA Interface I2C Bus SPI Bus ADC Programmable Counter Array (PCA)
whose address ends in 0h and 8h (as indicated by * in the table). Note: In the SFRs not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip and are reserved.
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Dual Data Pointers Data read access to the program memory and READ/WRITE access to the XRAM are executed using the data pointer DPTR as a 16-bit address register for indirect addressing mode. The DPTR consists of a high byte (DPH, 83H) and a low byte (DPL, 82H). Its intended function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers. The PSD33XX has two data pointers (DPTR0 and DPTR1), one of which is selected by Bit DPSEL0 in the Data Pointer Control Register DPTC. After reset, these registers are set to "00H." Only one DPTR is active at any time, and the selected PDTR resides in SFR address 83H and 82H. The DPTR which is not selected remains in the background and is not accessible by the CPU.
Data Pointer Control Register, DPTC (85H) The control register allows the DPTR to be selected manually, or automatically switching between the two data pointers. Bit DPSEL0 selects one of two pointers. The automatic switching between DPTR0 and DPTR1 is controlled by Bit AT (Auto Toggle). When Bit AT is set, Bit DPSEL0 is toggled automatically every time after the DPTR is accessed. Detailed description for register DPTC is shown in Table 4 and Table 5. The data pointer currently selected by the PSEL0 Bit can be modified, whereas the other data pointers are kept in the background and remain unchanged.
Table 4. Data Pointer Control Register, DPTC, Bit Definition (85H, Reset Value 00H)
Bit 7 - Bit 6 AT Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - Bit 0 DPSEL0
Table 5. Data Pointer Control Register Details
BIT 7 6 5-1 0 SYMBOL - AT - DPSE0 RW RW RW Reserved 0 = Manual Select Data Pointer 1 = Auto Toggle between DPTR0 and DPTR1 Reserved 0 = DPTR0 Selected 1 = DPTR1 Selected Definition
Note: Standard increment instruction on Register DPTC can be used to toggle Bit DPSEL0.
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Data Pointer Mode Register, DPTM (86H) The PSD33XX provides automatic increment or decrement of content of the working DPTR through the DPTM register. The content of the working DPTR is modified at the access time. De-
tailed description for DPTM is shown in Table 6 and Table 7. The automatic decrement or increment function in the DPTM Register is effective only for the MOVX instruction.
Table 6. Data Pointer Mode Register, DPTM Bit Definition (86H, Reset Value 00H)
Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 MD11 Bit 2 MD10 Bit 1 MD01 Bit 0 MD00
Table 7. Data Pointer Mode Register Details
BIT 7-4 SYMBOL - RW Reserved DPTR1 Mode Bits 00: DPTR1 No Change 01: Reserved 10: Auto Increment 11: Auto Decrement DPTR0 Mode Bits 00: DPTR0 No Change 01: Reserved 10: Auto Increment 11: Auto Decrement Definition
3-2
MD[11:10]
RW
1-0
MD[01:00]
RW
Debug Unit The MCU Module has a Debug Unit which supports debugging functions that are required in new PC board development. The JTAG port in the PSD33XX is responsible for communications between the host development system and the Debug Unit. The basic debugging functions supported include: - Halt or Start CPU execution - Reset the CPU - Single Step
- Four breakpoints, breaks on address/data - Debug Interrupt to CPU at breakpoint - Program tracing - READ/WRITE to SFR, PC and Memory The Debug pin can be configured in the host system to generate an output pulse for external triggering when a break condition is met. It can also be configured as an event input to the breakpoint logic in the Debug Unit. If not used, this pin should be pulled high.
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INTERRUPT SYSTEM There are interrupt requests from 10 sources as follows: s Debug Interrupt s INT0 External Interrupt s UART0 and UART1 Interrupt s Timer 0 Interrupt 2 s I C Interrupt s INT1 External Interrupt s ADC Interrupt s Timer 1 Interrupt s SPI Interrupt s Timer 2 Interrupt s PCA Interrupt External Int0 - The INT0 can be either level-active or transition-active depending on Bit IT0 in register TCON. The flag that actually generates this interrupt is Bit IE0 in TCON. - When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated. - If the interrupt was level activated then the interrupt request flag remains set until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. Timer 0 and 1 Inputs - Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1 which are set by an overflow
of their respective Timer/Counter registers (except for Timer 0 in Mode 3). - These flags are cleared by the internal hardware when the interrupt is serviced. Timer 2 Interrupt - Timer 2 Interrupt is generated by TF2 which is set by an overflow of Timer 2. This flag has to be cleared by the software - not by hardware. - It is also generated by the T2EX signal (Timer 2 External Interrupt P1.1) which is controlled by EXEN2 and EXF2 Bits in the T2CON register. I2C Interrupt - The interrupt of the I2C is generated by Bit INTR in the register S1STA. - This flag is cleared by hardware. External Int1 - The INT1 can be either level-active or transition-active, depending on Bit IT1 in register TCON. The flag that actually generates this interrupt is Bit IE1 in TCON. - When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to, but only if the interrupt was transition-activated. - If the interrupt was level-activated, then the interrupt request flag remains set until the requested interrupt is actually generated. It then has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated.
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ADC Interrupt - The ADC unit generates an interrupt when conversion is completed and AINTEN Bit of the ACON register is set. - After the interrupt is served, software needs to clear the interrupt flag AINTF. PCA Interrupt - Each of the 6 TCMs can generate a "match or capture" interrupt when enabled. The two 16bit counters can also generate two counter overflow interrupts. - The 8 PCA interrupts are "ORed" to generate one interrupt to the CPU. - After serving the interrupt, the software has to clear the flag in the Status register. SPI Interrupt - The SPI can generate interrupt when the receive buffer is full and the transmission buffer is empty. - An interrupt can also be generated at the end of transmission or receive overrun. UART Interrupt - The UART Interrupt is generated by RI (Receive Interrupt) or TI (Transmit Interrupt). - When the UART Interrupt is generated, the corresponding request flag must be cleared with software. The interrupt service routine will have to check the various UART registers to determine the source and clear the corresponding flag. - Both UARTs are identical, except for the additional interrupt controls in the Bit 4 of the additional interrupt control registers (A7H, B7H). Debug Interrupt - The Debug unit generates an interrupt when a Breakpoint condition is met. - The interrupt has the highest priority. After the interrupt is served, the software needs to clear the interrupt flag in the status register.
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Figure 7. Interrupt System
Interrupt Sources Debug P riority IE/IEA IP/IP A High Low
Ext INT0 Timer 0 Ext INT1
Timer 1
UART0
Interrupt Polling Sequence
Timer 2
SP I
Reserved
I2C
ADC
P CA
UART1
Global Enable
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Interrupt Priority Structure Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are defined by the Interrupt Priority special function registers IP and IPA. 0 = low priority 1 = high priority A low priority interrupt may be halted by a high priority level interrupt. A high priority interrupt routine cannot be halted by any other interrupt source. If two interrupts of different priority occur simultaneously, the higher priority level request is serviced. If requests are of the same priority and are Table 8. Priority Level
Priority 0 (Highest) 1 2 3 4 5 6 7 8 9 10 11 12 SOURCE DEBUG ExtINT0 Timer 0 ExtINT1 Timer 1 UART0 Timer 2 + EXF2 SPI Reserved I2C ADC PCA UART1 VECTOR ADDRESS 0063H 0003H 000BH 0013H 001BH 0023H 002BH 0053H 0033H 0043H 003BH 005BH 004BH
received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level, there is a second priority structure determined by the polling sequence. Interrupts Enable Structure Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable special function register IE and IEA. All interrupt sources can also be globally disabled by clearing Bit EA in the IE register.
Table 9. Interrupt SFR
SFR Addr A7 A8 B7 B8 Reg Name IEA IE IPA IP Bit Register Name 7 ADC EA PADC - 6 SPI EDB PSPI PDB 5 PCA ET2 PPCA PT2 4 ES1 ES0 PS1 PS0 3 - ET1 - PT1 2 - EX1 - PX1 1 EI2C ET0 PI2C PT0 PX0 EX0 0 Reset Value 00 00 00 00 Comments Interrupt Enable (2nd) Interrupt Enable Interrupt Enable (2nd) Interrupt Priority
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Table 10. Interrupt Enable SFR IE Bit Definition (A8H)
BIT SYMBOL FUNCTION Disable all interrupts. 0 = No interrupt will be acknowledged 1 = Each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Debug Unit Interrupt Enable Timer 2 Interrupt UART0 Interrupt Enable Timer 1 Interrupt Enable External Interrupt (INT1) Enable Timer 0 Interrupt Enable External Interrupt (INT0)
7
EA
6 5 4 3 2 1 0
EDB ET2 ES0 ET1 EX1 ET0 EX0
Table 11. Interrupt Enable Addition SFR IEA Bit Definition (A7H)
BIT 7 6 5 4 3 2 1 0 SYMBOL EADC ESPI EPCA ES1 - - EI2C - ADC Interrupt SPI Interrupt Programmable Counter Array Interrupt UART1 Interrupt Reserved Reserved Enable I2C Interrupt Reserved FUNCTION
Table 12. Interrupt Priority Level SFR IP Bit Definition (B8H)
BIT 7 6 5 4 3 2 1 0 SYMBOL - PDB PT2 PS0 PT1 PX1 PT0 PX0 Reserved Debug Interrupt Level Timer 2 Interrupt priority level UART0 Interrupt priority level Timer 1 Interrupt priority level External Interrupt (INT1) priority level Timer 0 Interrupt priority level External Interrupt (INT0) priority level FUNCTION
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Table 13. Interrupt Priority Level Addition SFR IPA Bit Definition (B7H)
BIT 7 6 5 4 3 2 1 0 SYMBOL PADC PSPI PPCA PS1 - - PI2C - ADC Interrupt priority level SPI Interrupt priority level PCA Interrupt level UART1 Interrupt priority level Not used Not used I2C Interrupt priority level Reserved FUNCTION
POWER SAVINGS MODES Three software-selectable modes of reduced power consumption are implemented. s Idle Mode s Power-down Mode s Reduced Frequency Mode Idle Mode Function Activity The following functions are switched off when the microcontroller enters the Idle Mode: - CPU (halted - waiting for interrupt to exit halt)
The following functions remain active during Idle Mode (except when disabled by the control registers). Some of these functions may generate an interrupt or reset and thus terminate the Idle Mode. - External Interrupts - Timer 0, Timer 1 and Timer 2 - Watchdog Timer - ADC - I2C Bus Interface - UART0 and UART1 - ADC - SPI - PCA (PWM)
Table 14. Port Status at Power-saving Mode
Mode Idle Power-down Ports 1, 3, 4 Maintain Data Maintain Data PCA Active Disable SPI Active Disable I2C Active Disable ADC Active Disable
Table 15. Bus Signals at Power-down and Idle Mode
Mode Idle Power-down ALE 0 0 PSEN_ 1 1 RD_ 1 1 WR_ 1 1 AD0-7 FF FF A8-15 FF FF
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Idle Mode The instruction that sets PCON.0 is the last instruction executed in the normal operating mode before Idle Mode is activated. Once in the Idle Mode, the CPU status is preserved in its entirety: Stack pointer, Program counter, Program status word, Accumulator, RAM, and All other registers maintain their data during Idle Mode. There are three ways to terminate the Idle Mode: - Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating Idle Mode. The interrupt is serviced, and following return from interrupt instruction, RETI, the next instruction to be executed will be the one which follows the instruction that wrote a logic '1' to PCON.0.
- External hardware reset: the hardware reset is required to be active for two machine cycles to complete the RESET operation. - Internal reset: the microcontroller restarts after 3 machine cycles in all cases. Power-down Mode The instruction that sets PCON.1 is the last executed prior to going into the Power-down Mode. Once in Power-down Mode, the oscillator is stopped. The contents of the on-chip RAM and the Special Function Register are preserved. The Power-down Mode can be terminated by an external RESET.
Table 16. PCON Register Bit Definition (87H, Reset Value 00H)
BIT 7 SYMBOL SMOD0 Baud Rate Double Bit (UART0) 0 = No Doubling 1 = Doubling Baud Rate Double Bit for 2nd UART (UART1) 0 = No Doubling 1 = Doubling Disable LVD by setting this bit. 0 = Enable 1 = Disable Power-on reset sets this bit to '1.' See SUPERVISORY, page 31 for details. 0 = Clear with software 1 = Set by power-on reset generated by Supervisory circuit Received Clock Flag (UART1) Transmit Clock Flag (UART1) Activate Power-down Mode 0 = Exit from Power-down 1 = Enter into Power-down Activate Idle Mode 0 = Exit from Idle Mode 1 = Enter into Idle Mode FUNCTION
6
SMOD1
5
LVD
4 3 2 1
POR RCLK1(1) TCLK1(1) PD
0
IDL
Note: 1. See the T2CON Register (Table 38, page 38) for details of the flag description.
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REDUCED FREQUENCY MODE The MCU consumes less power at lower clock frequency than at maximum frequency. The MCU can reduce the clock frequency by dividing the fOSC with the divider as defined in CCON0 Register (see Figure 8). This mode allows the MCU to remain active while consuming less power at a slower speed. By changing back to the original diFigure 8. Clock Generation Logic
PCON[1] : Power Down Buffer XTAL1 XT AL1 Q XTAL1 / 2 STALL CP UCLK (CPU, WDT, IO_PORT) MUX PCON[0]: IDLE
vider the MCU returns to normal mode. See CLOCK GENERATION, page 25 for more information. In Reduced Frequency Mode, the Peripherals can still be functional at normal fOSC frequency.
XTAL1 / 4 Q * * * XTAL1 / 2048 Q [Clock Divider] CPUPS
CP UCLK_nonstop (DBG, IRU) CP U CLK_muxout P FQCLK (PFQ) OSCCLK (TIMER0/1/2, UART0/1, P CA0/1, SP I,ADC)
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Note: 1. XTAL can be divided by 2 to 2048.
CLOCK GENERATION The clock unit uses the external crystal oscillator as a reference input clock, whose frequency is denoted by FOSC. Based on the Frequency Selection Control registers (CCON0), the clock unit generates the following clocks: CPUCLK. A clock for CPU and CPU-tightly-related peripherals (e.g., JTAG, WDT, IO_PORT). This clock is disabled in both the Power-down Mode and the Idle Mode. The frequency of CPUCLK is fCPU, which is obtained based on the fOSC, CPUPS[2:0], and internal signals Idle, and Stall. When 'Idle' is 1, fCPU is 0MHz. Otherwise, fCPU is a function of fOSC, CPUPS[2:0], and Stall. The Stall signal is generated from the Pre-fetch Queue (PFQ) block when the requested program code is not prepared in PFQ yet. CPUCLK is alive after a
breakpoint match or when the CPU is put in the halt state by the Debug Unit. CPUCLK_nonstop. A clock for CPU-loosely-related peripherals (e.g., Debug, Interrupt). This clock is the same as CPUCLK, except this clock is alive in Idle Mode. PFQCLK. A clock for PFQ. This clock is same as CPUCLK except that this is alive even in Idle Mode or when the CPU is stalled. OSCCLK. A clock for non-CPU related peripherals (e.g., TIMER0/1/2, UART0/1, PCA0/1, SPI). The frequency of OSCCLK is fOSC, which is obtained from the external clock input. This clock is disabled only in the Power-down Mode. The clock status is summarized in Table 17, page 26.
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Table 17. Clock Status
Power-saving Modes Name CPUCLK CPUCLK_nonstop PFQCLK JTAGCLK OSCCLK(1) Modules NORMAL CPU, JTAG, WDT, IO_PORT Debug, Interrupt PFQ JTAG TIMER0/1/2, UART0/1, PCA0/1, SPI, I2C, ADC ON ON ON ON ON IDLE OFF PD OFF OFF OFF OFF OFF fCPU fCPU fCPU fJTAG fOSC Freq.
Note: 1. OSCCLK is the output of the crystal oscillator.
CPU CLOCK CONTROL REGISTER The CPU Clock frequency is controlled by the CCON0 Register. The CPU is running at full frequency at power-up. The CPU Clock frequency can be changed any time by writing to the CPUPS Bits in the CCON0 register. After writing to the CCON0, the CPU Clock will be switched to the
new frequency immediately. The CPU Clock can be reduced by dividing the fOSC by 2 to 2048. When the CPU is running at reduced clock frequency and the CPUAR Bit is set, it allows the CPU Clock to return to full frequency immediately when any interrupt occurs. This is achieved by automatically changing the CPUPS Bits to '000.'
Table 18. CCON0 Register Bit Definition (0F9H, Reset Value 10H)
Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 DBGCE Bit 3 CUPAR Bit 2 Bit 1 CPUPS[2:0] Bit 0
Table 19. CCON0 Register Bit Definition Details
BIT 7-5 SYMBOL - RW Reserved Debug Address Comparison Enable 0 = DBG Address Comparison is disabled 1 = DBG Address Comparison is enabled (Default during the reset period.) After reset, this bit is set to enable the Debug Unit's Address Comparison feature for debugging purposes. This bit should be set to '0' if the debugging function is not needed. Automatic CPU Clock Recovery 0 = There is no change of CPUPS[2:0] when an interrupt occurs. 1 = CPUPS[2:0] becomes 3'b000 whenever any interrupt occurs. CPUCLK Pre-Scaler 000: fCPU = fOSC (Default during the reset period) 001: fCPU = fOSC/2 010: fCPU = fOSC/4 011: fCPU = fOSC/8 100: fCPU = fOSC/16 101: fCPU = fOSC/32 110: fCPU = fOSC/1024 111: fCPU = fOSC/2048 Definition
4
DBGCE
RW
3
CPUAR
RW
2:0
CPUPS
RW
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OSCILLATOR The oscillator circuit of the PSD33XX Devices is a single stage, inverting amplifier in a Pierce oscillator configuration. The circuitry between XTAL1 and XTAL2 is basically an inverter biased to the transfer point. Either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuit. Both are operated in parallel resonance. XTAL1 is the high gain amplifier input, Figure 9. Oscillator
and XTAL2 is the output. To drive the PSD33XX Devices externally, XTAL1 is driven from an external source and XTAL2 left open-circuit. The PSD33XX can run at maximum 40MHz clock. The CPU clock frequency can be configured in the CCON0 Register. However, the I2C bus requires a minimum 8MHz clock to be functional.
XTAL1
XTAL2
XTAL1
XTAL2
8 to 40 MHz External Clock
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I/O PORTS (MCU MODULE) The MCU Module has three ports: Port 1, Port 3, and Port 4 (see Table 20). (Refer to the PSD MODULE, page 65 and I/O PORTS (PSD MODULE), page 84). The ports support: s General Purpose I/O s Alternate peripheral functions s 5V tolerant s High current on Port 4 The 80-pin PSD33XX also has two ports in the MCU Module that are dedicated for the external MCU address and data bus. Ports 1, 3, and 4 are the same as in the standard 8032 microcontrollers, Table 20. I/O Port Functions
Port Name Port 1 General Purpose I/O GPIO
with the exception of the additional special peripheral functions. All ports are bi-directional. Pins which are not configured as Alternate functions are normally bi-directional I/O. The following SFR registers are used to control the mapping of alternate functions onto the I/O Port Bits (see Table 21 and Table 22). Port 1 and 4 alternate functions are controlled using the PXSFS1 registers. Port 3 alternate functions are controlled using the P3SFS register. After reset, the port SFR registers are cleared and are defaulted to general I/O.
Alternate 1 Function Timer 2 - Pins 0, 1 UART1 - Pins 2, 3 SPI - Pins 4.. 7 UART0 - Pins 0, 1 Interrupt - Pins 2, 3 Timers - Pins 4, 5 I2C - Pins 6, 7 PCA0 - Pins 0.. 3 PCA1 - Pins 4-7
Alternate 2 Function ADC - PIns 0.. 7
Port 3
GPIO
None
Port 4
GPIO
Timer 2 - Pins 0, 1 UART1 - Pins 2.. 3 SPI - Pins 4.. 7
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Port 1 Register P1SFS0, Port 1 Register P1SFS1 P1SFS0 Register Bits 0.. 7 definition (see Table 21): 0 = Select pin as GPIO 1 = Select pin as Alternate function
When the bit in the P1SFS0 register is '1,' alternate peripheral functions are assigned to the pin. The new P1SFS1 register bit further selects which one of the alternate function to be enabled. Table 22 shows the alternate functions assigned to port 1 and how it can be selected.
Table 21. Port 1 Register P1SFS0 (8EH, Reset Value 00H)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 = Port 1.7 0 = Port 1.6 0 = Port 1.5 0 = Port 1.4 0 = Port 1.3 0 = Port 1.2 0 = Port 1.1 0 = Port 1.0 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate
Table 22. Port 1 Register P1SFS1 (8FH, Reset Value 00H)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2
Port 3 Configuration Register Port 3 configuration is compatible to standard 8032, including alternate function pin assignments as shown in Table 23. Port 4 Configuration Register Port 4 has two registers: P4SFS0 Bit = 0 configures pin as GPIO and Bit = 1 configures pin as alternate function. P4SFS1 Bit determines which alternate function is to be enabled (see Table 24). The alternate 2 functions on Port 4 are the same as the alternate function 1 of Port 1. If an identical alternate function is assigned to both ports, the
Port 1 function has priority and the Port 4 function is disabled. P4SFS0 Register Bits 0.. 7 definition: 0 = Select pin as GPIO 1 = Select pin as Alternate function Port 4 High Current Option Port 4 is a high current port (see Table 25). All 8 of the port pins are capable of a sink/source value of 10mA per pin in alternative function mode. The pins can sink 10mA in GPIO Mode. See the DC AND AC PARAMETERS, page 98, for VOL/VOH specification on Port 4.
Table 23. Port 3 Register P3SFS (91H, Reset Value 00H)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 = Port 3.7 0 = Port 3.6 0 = Port 3.5 0 = Port 3.4 0 = Port 3.3 0 = Port 3.2 0 = Port 3.1 0 = Port 3.0 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate
Table 24. Port 4 Register P4SFS0 (92H, Reset Value 00H)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 = Port 4.7 0 = Port 4.6 0 = Port 4.5 0 = Port 4.4 0 = Port 4.3 0 = Port 4.2 0 = Port 4.1 0 = Port 4.0 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate 1 = Alternate
Table 25. Port 4 Register P4SFS1 (93H, Reset Value 00H)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 0 = Alternate1 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2 1 = Alternate2
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MCU MEMORY BUS INTERFACE The MCU Module reads or writes to the PSD Module through the MCU memory bus. The Memory Bus is also available to external pins in the 80-pin package. The 8-bit MCU bus consists of standard 8032 bus signals. READ Bus Cycle (Code or XDATA) The READ bus cycle reads 8 bits per bus cycle and is identical for both the Program Fetch (PSEN) and Data Read (RD) in terms of timing and function. When the PSD Module is selected and either PSEN or RD is active, the PSD Module will drive data D0-D7 of the MCU bus. For program fetch, the MCU keeps the byte in the Pre-fetch Buffer. As for the XDATA READ bus cycle, the MCU routes the data byte to the CPU core directly. The READ bus cycle timing and length is controlled by the BUSCON Register. WRITE Bus Cycle (XDATA) The MCU writes one byte per bus cycle. The timing and length of the WRITE Bus Cycle is controlled by the BUSCON Register, which can be programmed by the software.
Bus Control Register (BUSCON) The PSD33XX has a programmable bus interface where the user can specify the length of a bus cycle. Based on the PQF Clock frequency, the number of clocks in a bus cycle can be changed to maximize data transfer rate (see Table 27). The PSD33XX defaults to 6 PFQ clock for all READ and WRITE bus cycles after reset. Table 28 shows the minimum number of PFQ clocks in a bus cycle that are required for different PFQ Clock frequencies. In addition, the BUSCON allows the user to set bits to turn on/off the Prefetch Queue and Branch Cache. In some real time applications, turning off the queue and cache provides determinable execution. The user may also wish to turn the queue and cache off during debugging.
Table 26. BUSCON Register Bit Definition (9DH, Reset Value 2BH)
Bit 7 EPFQ Bit 6 EBC Bit 5 WRW1 Bit 4 WRW0 Bit 3 RDW1 Bit 2 RDW0 Bit 1 CW1 Bit 0 CW0
Table 27. Number of PFQ Clocks Required to Optimize Bus Transfer Rate
PFQ Clock Frequency 25-40MHz 8-24MHz Code Data 3V(1) 5 3 5V(1) 4 3 3V(1) 5 4 READ Data 5V(1) 4 4 WRITE Data 3V(1) 5 4 5V(1) 4 4
Note: 1. VDD of the PSD Module
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Table 28. BUSCON Register Bit Definition Details
Register Bit Definition Code Fetch bus cycle: When PFQ fetches code, 2'b00: The code read from memory takes 3 PFQCLK clocks 2'b01: The code read from memory takes 4 PFQCLK clocks 2'b10: The code read from memory takes 5 PFQCLK clocks 2'b11: The code read from memory takes 6 PFQCLK clocks (default) XDATA READ bus cycle: 2'b00: The code read from XDATA takes 4 PFQCLK clocks 2'b01: The code read from XDATA takes 5 PFQCLK clocks 2'b10: The code read from XDATA takes 6 PFQCLK clocks (default) 2'b11: The code read from XDATA takes 7 PFQCLK clocks XDATA WRITE bus cycle 2'b00: The code read from XDATA takes 4 PFQCLK clocks 2'b01: The code read from XDATA takes 5 PFQCLK clocks 2'b10: The code read from XDATA takes 6 PFQCLK clocks (default) 2'b11: The code read from XDATA takes 7 PFQCLK clocks Enable Branch Cache 0 = BC is disabled (default) 1 = BC is enabled Enable Prefetch Queue 0 = PFQ is disabled (default) 1 = PFQ is enabled
CW1.. CW0
RDW1.. RDW0
WRW1.. WRW0
EBC
EPFQ
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SUPERVISORY There are four ways to invoke a reset and initialize the PSD33XX Devices: s Via the external RESET pin s Via the internal LVR Block. s Via Watch Dog timer Figure 10. RESET Configuration
RESET Input Pin Noise Cancel WDT LVR Debug 10ms(1) Timer
AI07849
Each RESET source will cause an internal reset signal to be active. The CPU responds by executing an internal reset and puts the internal registers in a defined state. This internal reset is also routed as an active low reset input to the PSD Module.
CPU Clock Sync
CPU & PERI.
S R
Q
PSD_RST "Active Low signal"
Note: 1. 10ms at 40MHz, 50ms at 8MHz.
External Reset The RESET pin is connected to a Schmitt trigger for noise reduction. A RESET is accomplished by holding the RESET pin LOW for at least 1ms at power-up while the oscillator is running. Refer to AC specification on other RESET timing requirements. Low VCC Voltage Reset An internal reset is generated by the LVR circuit when the VCC drops below the reset threshold. After VCC returns to the reset threshold, the RESET signal will remain asserted for 10ms before it is released. On initial power-up the LVR is enabled (default). After power-up the LVR can be disabled via the LVREN Bit in the PCON Register. Note: The LVR logic is functional in both the Idle and Power-down Modes. The reset circuit resides in the MCU Module which operates at 3.3V VCC. The reset threshold will always be: 2.5V +/-0.2V for all PSD33XX devices. This logic supports approximately 0.1V of hysteresis and 1s noise-cancelling delay.
Watchdog Timer Overflow Reset The Watchdog timer generates an internal reset when its 24-bit counter overflows. See WATCHDOG TIMER, page 32 for details. Debug Unit Reset The Debug Unit can generate a reset to the Supervisory circuit for debugging purpose. Under normal operation, this reset source is disabled. Reset Output The output of the reset logic resets the MCU, it also drives a PSD_Reset signal (active low) which is connected to the Reset Input on the PSD Module. The output of the reset logic remains asserted for a minimum of approximately 10ms. This time base is calculated by counting the fOSC at 40Mhz to last a minimum of 10ms at 40Mhz. The time will be longer as the fOSC is lower. Power-up Reset At power up, the internal reset generated by the LVD circuit is latched as a '1' in the PCON register (Bit POR). Software can read this bit and determine whether the last CPU reset is a power up or warm reset. This bit must be cleared with software.
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WATCHDOG TIMER The hardware watchdog timer (WDT) resets the PSD33XX Devices when it overflows. The WDT is intended as a recovery method in situations where the CPU may be subjected to a software upset. To prevent a system reset the timer must be reloaded in time by the application software. If the processor suffers a hardware/software malfunction, the software will fail to reload the timer. This failure will result in a reset upon overflow thus preventing the processor running out of control. In the Idle Mode the watchdog timer and reset circuitry remain active. The WDT consists of a 24-bit counter, the Watchdog Timer RESET (WDRST) Figure 11. Watchdog Counter
23 8 bit WDTRST 15 8 bit 7 8 bit
AI07850
SFR, and the Watchdog Key Register (WDKEY). Since the WDKEY register is loaded with 55h after reset, the Watchdog is disabled until it is enabled by the software. Watchdog Counter The 24-bit counter runs on machine cycle (4 fOSC clocks) and has a WDT reset period of about 1.6 seconds (see Figure 11). The 8th MSB of the counter is loaded from the Watch Dog Timer Clear Register (WDRST). By writing to the WDRST register, the user can change the WDT reset period. The 24-bit counter overflows when it reaches FFFFFFh.
0
mach in e cycle = ( 4T OSC + T STALL ) 1 wh ere, T OSC = ------------------- = 0.025 us = 25ns 40MHz TSTALL: the average waiting time due to PFQ/BC stall For example, when tSTALL is '0' and tOSC is 25ns, the total required cycle (to reach the overflow of the 24bit counter that is clocked at machine cycle) is as below: 2
24
x2
2
=2
26
= 2 x2
6
20
= 64 x ( 2
10 2
)
= 64 million ( OSCcycle )
Therefore, the reset period is: rese t p erio d = 64M x 25n s = 1.6 s
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WDT Registers WDTKEY Register - When this SFR is written as #55h, the WDT is disabled. Otherwise, writing any other values to the register will disable the WDT. Since the reset value of WDTKEY is #55h, the WDT is disabled at reset. The WDT is disabled after the reset that is generated by the WDT counter overflow. - When the WDT is disabled, the 24-bit counter is cleared. Therefore, the new value of WDTRST must be written into the 24-bit counter after the WDT is enabled. - In Idle Mode, the oscillator continues to run. To prevent the WDT from resetting the processor while in Idle, the user should
always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle Mode. WDTRST Register - When this SFR is written as a value, the value is loaded into the upper 8 bits of 24-bit counter in WDT. And, the lower 16 bits are cleared. - If the user write "WDTRST" by '04h, then the value of the 24-bit counter changes from 040000, 040001, 040002, ..., FFFFFF, then generates the WDT reset.
Table 29. WDKEY: Watchdog Timer Key Register (0AEH, Reset Value 55H)
Bit 7 WDKEY7 Bit 6 WDKEY6 Bit 5 WDKEY5 Bit 4 WDKEY4 Bit 3 WDKEY3 Bit 2 WDKEY2 Bit 1 WDKEY1 Bit 0 WDKEY0
Table 30. WDKEY: Watchdog Timer Key Register Details
Register Bit WDKEY7.. 0 Definition Enable or disable watchdog timer. Writing to WDKEY with data pattern 01010101 (= 55h) will disable the watchdog timer. Other data: enables the watchdog timer.
Table 31. WDRST: Watchdog Timer Clear Register (0A6H, Reset Value 00H)
Bit 7 WDRST7 Bit 6 WDRST6 Bit 5 WDRST5 Bit 4 WDRST4 Bit 3 WDRST3 Bit 2 WDRST2 Bit 1 WDRST1 Bit 0 WDRST0
Table 32. WDRST: Watchdog Timer Clear Register Details
Register Bit WDRST[7.. 0] Definition To reset watchdog timer, write any value to this register. This value is loaded to the 8th most significant bits of the 24-bit counter.
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TIMER/COUNTERS (TIMER0, TIMER1, AND TIMER The PSD33XX Devices has three 16-bit Timer/ Counter registers: Timer 0, Timer 1 and Timer 2. All of them can be configured to operate either as timers or event counters and are compatible with standard 8032 architecture (see Table 33). In the "Timer" function, the register is incremented every 1/12 of the oscillator frequency (fOSC). In the "Counter" function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled by the counter. When the samples show a high in one machine cycle and a low in the another, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. The maximum 2) count rate is 1/24 of the fOSC as in standard 8032. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. In addition to the "Timer" or "Counter" selection, Timer 0 and Timer 1 have four operating modes from which to select. Timer 0 and Timer 1 The "Timer" or "Counter" function is selected by control bits C/T in the Special Function Register, TMOD (see Table 34). These Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for Timers/ Counters. Mode 3 is different.
Table 33. TCON Register (88H, Reset Value 00H) - Timer 0, 1
Bit 7 TF1 Bit 6 TR1 Bit 5 TF0 Bit 4 TR0 Bit 3 IE1 Bit 2 IT1 Bit 1 IE0 Bit 0 IT0
Table 34. TCON Register Details - Timer 0, 1
Bit 7 6 5 4 3 2 1 0 Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Function Timer 1 Overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine Timer 1 Run Control Bit. Set/cleared with software to turn Timer/Counter on or off Timer 0 Overflow flag. Set by hardier on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine Timer 0 Run Control Bit. Set/cleared with software to turn Timer/Counter on or off Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed Interrupt 1 Type Control Bit. Set/cleared with software to specify falling-edge/low-level triggered external interrupt Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed Interrupt 0 Type Control Bit. Set/cleared with software to specify falling-edge/low-level triggered external interrupt
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Mode 0. Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure 12 shows the Mode 0 operation as it applies to Timer 1. In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all '1s' to all '0s,' it sets the Timer Interrupt flag TF1. The counted input is enabled to the Timer when TR1 = 1 and either GATE = 0 or /INT1 = 1. (Setting GATE = 1 allows the Timer to be controlled by external input /INT1 to facilitate pulse width measurements). TR1 is a control bit in the Special Function Register TCON (TCON Control Register). GATE is in TMOD (see Table 35 and Table 36, page 37). The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Setting the run flag does not clear the registers. Mode 0 operation is the same for the Timer 0 as for Timer 1. Substitute TR0, TF0, and /INT0 for the corresponding Timer 1 signals in Figure 12. There are two different GATE Bits, one for Timer 1 and one for Timer 0. Mode 1. Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits. Figure 12. Timer/Counter Mode 0: 13-bit Counter Mode 2. Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 13, page 36. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset with software. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0. Mode 3. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 14. TL0 uses the Timer 0 control Bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the "Timer 1"Interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer on the counter (see Figure 14, page 36). With Timer 0 in Mode 3, an PSD33XX Devices can look like it has three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt.
fOSC
/ 12 C/T = 0 TL1 (5 bits) Control TH1 (8 bits) TF1 Interrupt
T1 pin
C/T = 1
TR1 Gate INT1 pin
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Figure 13. Timer/Counter Mode 2: 8-bit Auto-reload
fOSC
/ 12 C/T = 0 TL1 (8 bits) Control TF1 Interrupt
T1 pin
C/T = 1
TR1 Gate INT1 pin TH1 (8 bits)
AI06623
Figure 14. Timer/Counter Mode 3: Two 8-bit Counters
fOSC
/ 12 C/T = 0 TL0 (8 bits) Control TF0 Interrupt
T0 pin
C/T = 1
TR0 Gate INT0 pin
fOSC
/ 12 Control
TH0 (8 bits)
TF1
Interrupt
TR1
AI06624
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Table 35. TMOD Register (TMOD)
Bit 7 GATE Bit 6 C/T Bit 5 M1 Bit 4 M0 Bit 3 GATE Bit 2 C/T Bit 1 M1 Bit 0 M0
Table 36. TMOD Register Details
Bit 7 Symbol GATE Timer Function Gating control when set. Timer/Counter 1 is enabled only while INT1 pin is High and TR1 control pin is set. When cleared, Timer 1 is enabled whenever TR1 Control Bit is set Timer or Counter selector, cleared for timer operation (input from internal system clock); set for counter operation (input from T1 input pin) (M1,M0)=(0,0): 13-bit Timer/Counter, TH1, with TL1 as 5-bit prescaler (M1,M0)=(0,1): 16-bit Timer/Counter. TH1 and TL1 are cascaded. There is no prescaler. (M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH1 holds a value which is to be reloaded into TL1 each time it overflows (M1,M0)=(1,1): Timer/Counter 1 stopped Gating control when set. Timer/Counter 0 is enabled only while INT0 pin is High and TR0 control pin is set. When cleared, Timer 0 is enabled whenever TR0 Control Bit is set Timer or Counter selector, cleared for timer operation (input from internal system clock); set for counter operation (input from T0 input pin) Timer 0 (M1,M0)=(0,0): 13-bit Timer/Counter, TH0, with TL0 as 5-bit prescaler (M1,M0)=(0,1): 16-bit Timer/Counter. TH0 and TL0 are cascaded. There is no prescaler. (M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH0 holds a value which is to be reloaded into TL0 each time it overflows (M1,M0)=(1,1): TL0 is an 8-bit Timer/Counter controlled by the standard TImer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 Control Bits
6 5 4
C/T Timer 1 M1 M0
3
GATE
2 1
C/T M1
0
M0
Timer 2 Like Timers 0 and 1, Timer 2 can operate as either an event timer or as an event counter. This is selected by Bit C/T2 in the special function register T2CON. It has three operating modes: capture, autoload, and baud rate generator, which are selected by bits in the T2CON as shown in Table 37 and Table 38, page 38. In the Capture Mode there are two options which are selected by Bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter which upon overflowing sets Bit TF2, the Timer 2 Overflow Bit, which can be used to generate an interrupt. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes Bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an in-
terrupt. The Capture Mode is illustrated in Figure 15, page 39. In the Auto-reload Mode, there are again two options, which are selected by bit EXEN2 in T2CON (see Table 39, page 39). If EXEN2 = 0, then when Timer 2 rolls over it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2L and RCAP2H, which are preset with software. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2EX will also trigger the 16-bit reload and set EXF2. The Auto-reload Mode is illustrated in Standard Serial Interface (UART) Figure 16, page 40. The Baud Rate Generation Mode is selected by (RCLK, RCLK1)=1 and/or (TCLK, TCLK1)=1. It will be described in conjunction with the serial port.
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Table 37. T2CON: Timer/Counter 2 Control Register (C8H, Reset Value 00H))
Bit 7 TF2 Bit 6 EXF2 Bit 5 RCLK Bit 4 TCLK Bit 3 EXEN2 Bit 2 TR2 Bit 1 C/T2 Bit 0 CP/RL2
Table 38. T2CON Register Details
Bit 7 Symbol TF2 Function Timer 2 Overflow flag. Set by a Timer 2 overflow, and must be cleared with software. TF2 will not be set when either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2=1. When Timer 2 Interrupt is enabled, EXF2=1 will cause the CPU to vector to the Timer 2 Interrupt routine. EXF2 must be cleared with software Receive Clock flag (UART0). When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be used for the receive clock Transmit Clock flag (UART0). When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be used for the transmit clock Timer 2 External Enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2=0 causes Time 2 to ignore events at T2EX Start/Stop control for Timer 2. A logic 1 starts the timer Timer or Counter Select for Timer 2. Cleared for timer operation (input from internal system clock, tCPU); set for external event counter operation (negative edge triggered) Capture/Reload flag. When set, capture will occur on negative transition of T2EX if EXEN2=1. When cleared, auto-reload will occur either with TImer 2 overflows, or negative transitions of T2EX when EXEN2=1. When either (RCLK, RCLK1)=1 or (TCLK, TCLK1)=1, this bit is ignored, and timer is forced to auto-reload on Timer 2 overflow
6
EXF2
5
RCLK(1)
4
TCLK(1)
3 2 1
EXEN2 TR2 C/T2
0
CP/RL2
Note: 1. The RCLK1 and TCLK1 Bits in the PCON Register control UART1, and have the same function as RCLK and TCLK.
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Table 39. Timer/Counter 2 Operating Modes
T2CON Mode RxCLK or TxCLK 0 16-bit Autoreload 0 0 0 0 16-bit Capture 0 Baud Rate Generator Off 1 1 x 1 x x x 1 1 1 0 1 0 1 x CP/ RL2 0 0 0 0 1 TR2 1 1 1 1 1 T2CON EXEN P1.1 T2EX Remarks Internal reload upon overflow reload trigger (falling edge) Down counting Up counting 16-bit Timer/Counter (only up counting) Capture (TH2,TL2) (RCAP2H,RCAP2L) No overflow interrupt request (TF2) Extra External Interrupt (Timer 2) Timer 2 stops fOSC/12 fOSC/12 MAX fOSC/24 Input Clock External (P1.0/T2)
0 1 x x 0
x 0 1 x x x
MAX fOSC/24
fOSC/12 --
MAX fOSC/24 --
Note: = falling edge
Figure 15. Timer 2 in Capture Mode
fOSC
/ 12 C/T2 = 0 TL2 (8 bits) Control TH2 (8 bits) TF2
T2 pin
C/T2 = 1
TR2 Capture RCAP2L RCAP2H Timer 2 Interrupt
Transition Detector
T2EX pin Control
EXP2
EXEN2
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Figure 16. Timer 2 in Auto-Reload Mode
fOSC
/ 12 C/T2 = 0 TL2 (8 bits) Control TH2 (8 bits) TF2
T2 pin
C/T2 = 1
TR2 Reload RCAP2L RCAP2H Timer 2 Interrupt
Transition Detector
T2EX pin Control
EXP2
EXEN2
AI06626
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STANDARD SERIAL INTERFACE (UART) The PSD33XX Devices provide two standard 8032 UART serial ports. The first port (UART0) is connected to pin P3.0 (RxD0) and P3.1 (TxD0). The second port (UART1) is connected to pin P1.2 (RxD1) and P1.3(TxD1) or P4.2 and P4.3. The operation of the two serial ports are the same and are controlled by the SCON0 and SCON1 registers. The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receivebuffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF0 (or SBUF1 for the second serial port). Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0. Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the fOSC. Mode 1. 10 bits are transmitted (through TxD) or received (through RxD): a Start Bit (0), 8 data bits (LSB first), and a Stop Bit (1). On receive, the Stop Bit goes into RB8 in Special Function Register SCON. The baud rate is variable.
Mode 2. 11 bits are transmitted (through TxD) or received (through RxD): Start Bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a Stop Bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of '0' or '1.' Or, for example, the Parity Bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the Stop Bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. Mode 3. 11 bits are transmitted (through TxD) or received (through RxD): a Start Bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a Stop Bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming Start Bit if REN = 1. Serial Port Control Register The serial port control and status register is the Special Function Register SCON0 (SCON1 for the second port), shown in Table 40 and Table 41, page 42. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the Serial Port Interrupt Bits (TI and RI).
Table 40. Serial Port Control Register (SCON0 and SCON1)
Bit 7 SM0 Bit 6 SM1 Bit 5 SM2 Bit 4 REN Bit 3 TB8 Bit 2 RB8 Bit 1 TI Bit 0 RI
Note: 1. SCON0 (98H - UART0 Reset Value 00); SCON1 (D8H - UART1 Reset Value 00)
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Table 41. SCON0 and SCON1 Register Details
Bit 7 6 Symbol SM0 SM1 Enables the multiprocessor communication features in Mode 2 and 3. In Mode 2 or 3, if SM2 is set to '1,' RI will not be activated if its received 8th data bit (RB8) is '0.' In Mode 1, if SM2=1, RI will not be activated if a valid Stop Bit was not received. In Mode 0, SM2 should be '0.' Enables serial reception. Set with software to enable reception. Clear with software to disable reception. The 8th data bit that will be transmitted in Modes 2 and 3. Set or clear with software as desired In Modes 2 and 3, this bit contains the 8th data bit that was received. In Mode 1, if SM2=0, RB8 is the Snap Bit that was received. In Mode 0, RB8 is not used. Transmit Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the Stop Bit in the other modes, in any serial transmission. Must be cleared with software. Receive Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the Stop Bit in the other modes, in any serial reception (except for SM2). Must be cleared with software. See Table 42. Function
5
SM2
4 3 2
REN TB8 RB8
1
TI
0
RI
Table 42. UART Operating Table
SCON Mode SM0 0 0 SM1 0 fOSC/12 Serial data enters and exits through RxD. TxD outputs the shift clock. 8-bit are transmitted/received (LSB first) 8-bit UART 10 bits are transmitted (through TxD) or received (RxD). 9-bit UART 11 bits are transmitted (through TxD) or received (RxD) 9-bit UART Like Mode 2, except the variable baud rate. Baud Rate Description
1 2 3
0 1 1
1 0 1
Timer 1/2 overflow rate fOSC/32 or fOSC/64 Timer 1/2 overflow rate
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Baud Rates. The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = fOSC / 12 The baud rate in Mode 2 depends on the value of Bit SMOD = 0 (which is the value on reset), the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. Mode 2 Baud Rate = (2SMOD / 64) x fOSC In the PSD33XX Devices, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate. Using Timer 1 to Generate Baud Rates. When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Mode 1,3 Baud Rate = (2SMOD / 32) x (Timer 1 overflow rate) The Timer 1 Interrupt should be disabled in this application. The Timer itself can be configured for either "timer" or "counter" operation, and in any of its 3 running modes. In the most typical applications, it is configured for "timer" operation, in the Auto-reload Mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula: Mode 1,3 Baud Rate = (2SMOD / 32) x (fOSC / (12 x [256 - (TH1)])) One can achieve very low baud rates with Timer 1 by leaving the Timer 1 Interrupt enabled, and configuring the Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 Interrupt to do a 16-bit software reload. Figure 12, page 35 lists various commonly used baud rates and how they can be obtained from Timer 1. Using Timer/Counter 2 to Generate Baud Rates. In the PSD33XX Devices, Timer 2 selected as the baud rate generator by setting TCLK and/or RCLK (see Figure 12, page 35, Timer/ Counter 2 Control Register). Note: The baud rate for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer into its Baud Rate Generator Mode. The RCLK and TCLK Bits in the T2CON register configure UART0. The RCLK1 and TCLK1 Bits in the PCON register configure UART1. The Baud Rate Generator Mode is similar to the Auto-reload Mode, in that a roll over in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset with software. Now, the baud rates in Modes 1 and 3 are determined at Timer 2's overflow rate as follows: Mode 1,3 Baud Rate = Timer 2 Overflow Rate / 16 The timer can be configured for either "timer" or "counter" operation. In the most typical applications, it is configured for "timer" operation (C/T2 = 0). "Timer" operation is a little different for Timer 2 when it's being used as a baud rate generator. In this case, the baud rate is given by the formula: Mode 1,3 Baud Rate = fOSC/(32 x [65536 - (RCAP2H, RCAP2L)] where (RCAP2H, RCAP2L) is the content of RC2H and RC2L taken as a 16-bit unsigned integer. Timer 2 also may be used as the Baud Rate Generating Mode. This mode is valid only if RCLK + TCLK = 1 in T2CON or in PCON. Note: A roll-over in TH2 does not set TF2, and will not generate an interrupt. Therefore, the Timer Interrupt does not have to be disabled when Timer 2 is in the Baud Rate Generator Mode. Note: If EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt, if desired. Note: When Timer 2 is running (TR2 = 1) in "timer" function in the Baud Rate Generator Mode, one should not try to READ or WRITE TH2 or TL2. Under these conditions the timer is being incremented every state time, and the results of a READ or WRITE may not be accurate. The RC registers may be read, but should not be written to, because a WRITE might overlap a reload and cause WRITE and/or reload errors. Turn the timer off (clear TR2) before accessing the Timer 2 or RC registers, in this case.
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IRDA INTERFACE TO INFRARED TRANSCEIVER The PSD33XX provides an IrDA interface that meets the IrDA Specification. The IrDA Interface logic "pulse shaping" the UART1 (2nd UART) serial signal from a UART Frame to an IrDA standard IR Frame (and vise versa) that can be accepted by a standard IrDA Transceiver. When enabled and in transmitting mode, the IrDA Interface shortens the UART output signal to IrDA compatible electrical pulses. In receiving mode, the Interface stretches the IrDA transceiver signal to the proper bit rate to be received by the UART. The outputs of the IrDA Interface drive the IrDA Transceiver directly. The UART1 can operate in 4 modes, Mode 0 to Mode 3. The IrDA Interface supports Mode 1 (10 bits transmit - Start Bit, 8 data bits and 1 Stop Bit) only so as to be compatible with the IrDA format. The IrDA Interface supports baud rate generated by Timer 1 or Timer 2, but the Tx and Rx must be of the same baud rate. Figure 17. PSD33XX IrDA Interface
The features of the IrDA Interface are: Stretches the UART pulse to 1.627s; it supports IrDA pulse from 1.41s (Min) to 2,23s (Max) pulse or 3/16 bit pulse duration. s Support for baud rates from 1.2kHz to 115.2kHz s Direct interface to SIR transceiver from UART1 I/O pins (RxD1, TxD1) on Ports 1 or 4 s IRDACON Register bits select pulse duration and specify baud rate The IrDA Interface is disabled on power-up and is enabled by the IRDAEN Bit in the IRDACON Register (see Table 43 and Table 44, page 44). When it is disabled, the UART1's RxD and TxD bypass the IrDA Interface and are connected directly to the port pins. The IrDA Interface generates a 1.627s or 3/16 bit pulse width output when the bit is a '0' on the TxD line and stays '0' when the bit is a '1.'
s
SIRClk IrDA Interface
TxD1-IrDA IrDA Transceiver RxD1-IrDA
UART1 TxD RxD
uPSD33XX
AI07851
Table 43. IRDACON Register Bit Definition (CEH, Reset Value 0FH)
Bit 7 - Bit 6 IRDAEN Bit 5 PULSE Bit 4 CDIV4 Bit 3 CDIV3 Bit 2 CDIV2 Bit 1 CDIV1 Bit 0 CDIV0
Table 44. IRDACON Register Details
BIT 7 SYMBOL - RW Reserved IrDA Enable 0 = IrDA Interface is disabled 1 = IrDA is enabled, UART1 outputs are disconnected from Port 1 (or port 4) Definition
6
IRDAEN
RW
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BIT 5 4-0 SYMBOL PULSE CDIV[4:0] RW RW RW Definition IrDA Pulse Modulation Select 0 = 1.627s 1 = 3/16 bit time pulses Specify Clock Divider (see Table 45)
Baud Rate Select There will be two schemes for IrDA pulse modulation: 1. In the event of 3/16 bit time pulse modulation: At maximum baud rate of 115.2kHz, the 3/16 bit time pulse is 1.627s. 2. In case of 1.627s pulse modulation: To implement 1.627s pulse modulation, a prescaler is needed to generate a subrefernce Table 45. f SIRCLK Frequency
fOSC 40.0MHz 33.0MHz 30.0MHz 24.0MHz 16.0MHz 12.0MHz
clock (i.e, SIRClk) that is used to generate 1.627s pulse modulation. Even though the pulse width is 1.627s, the baud rate follows the configuration of UART1. Select a clock divider to generate a FSIRCLK clock close to 1.8432MHz. FSIRCLK = fOSC / (CDIV[4:0]) where CDIV[4:0] must be 4 or larger.
CDIV[4:0] (Clock divider) 22 18 16 13 9 7
fSIRCLK(1) 1.8181MHz 1.8333MHz 1.8750MHz 1.8461MHz 1.7777MHz 1.7142MHz
Note: 1. fSIRCLK at 1.8342MHz is needed to generate the 1.627s pulse.
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I2C INTERFACE There is a serial I2C port implemented in the PSD33XX Devices. The serial port supports the twin line I2C -bus and consists of a data line (SDA) and a clock line (SCL). Depending on the configuration, the SDA and SCL lines may require pull-up resistors. The system is unique because data transport, clock generation, address recognition, and bus control arbitration are all controlled by hardware. The I2C serial I/O has complete autonomy in byte handling and operates in 4 modes: s Master transmitter s Master receiver s Slave transmitter s Slave receiver Figure 18. I2C Bus Block Diagram
7 Slave Address 7 SDA Arbitration + Sync. Logic Shift Register Internal Bus 0 0
These functions are controlled by the I2C SFRs: S1CON: the Control register - control of byte handling and the operation of 4 mode S1STA: the Status register - contents of its register may also be used as a vector to various service routines. S1DAT: Data Shift register. S1ADR: Slave Address register. Slave address recognition is performed by On-Chip Hardware. Table 48, page 47 shows the divisor values and the I2C bit rate for some common fOSC frequencies.
SCL 7
Bus Clock Generation 0 Control Register 7 Status Register 0
AI07852
I2C Registers Definition Table 46. Serial Control Register S1CON (DCH, Reset Value 00H)
Bit 7 CR2 Bit 6 ENI1 Bit 5 STA Bit 4 STO Bit 3 ADDR Bit 2 AA Bit 1 CR1 Bit 0 CR0
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Table 47. S1CON Register Details
Bit 7 6 Symbol CR2 ENI1 Function This bit, along with Bits CR1and CR0 determines the serial clock frequency when SIO is in the Master Mode. Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are in the high impedance state. START flag. When this bit is set, the SIO H/W checks the status of the I2C bus and generates a START condition if the bus is free. If the bus is busy, the SIO will generate a repeated START condition when this bit is set. When a START condition is detected on the I2C Bus, the I2C hardware clears the STA flag. Note: If this bit is set during an interrupt service, the START condition occurs after the interrupt service. STOP flag. With this bit set while in Master Mode a STOP condition is generated. When a STOP condition is detected on the I2C bus, the I2C hardware clears the STO flag. Note: If this bit is set during an interrupt service, the STOP condition occurs after the interrupt service. This bit is set when address byte was received. Must be cleared with software. Acknowledge enable signal. If this bit is set, an acknowledge (low level to SDA is returned during the acknowledge clock pulse on the SCL line when: s Own slave address is received; s A data byte is received while the device is programmed to be a Master Receiver; s A data byte is received while the device is a selected Slave Receiver; and s When this bit is reset, no acknowledge is returned. SIO release SDA line as high during the acknowledge clock pulse. These two bits, along with the CR2 Bit determine the serial clock frequency when SIO is in the Master Mode.
5
STA
4
STO
3
ADDR
2
AA
1, 0
CR1, CR0
Table 48. Selection of the Serial Clock Frequency SCL in Master Mode
CR2 0 0 0 0 1 1 1 1 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 fOSC Divisor 12MHz 16 24 30 60 120 240 480 960 375 250 200 100 50 25 12.5 6.25 Bit Rate (kHz) @ fOSC 24MHz 750 500 400 200 100 50 25 12.5 36MHz X(1) 750 600 300 150 75 37.5 18.75 40MHz X(1) 833 666 333 166 83 41 20
Note: 1. These values are beyond the supported bit rate.
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Serial Status Register (S1STA) S1STA is a "Read only" register (except Bit 5 INTR, see Table 49). The contents of this register may be used as a vector to a service routine. This optimized the response time of the software and consequently that of the I2C-bus. The status codes for all possible modes of the I2C bus interface are given Table 50. This flag is set, and an interrupt is generated after any of the following events occur. 1. Own slave address has been received during AA = 1: ack_int 2. The general call address has been received while GC(S1ADR.0) = 1 and AA = 1
3. A data byte has been received or transmitted in Master Mode (even if arbitration is lost): ack_int 4. A data byte has been received or transmitted as selected slave: ack_int 5. A Stop condition is received as selected slave receiver or transmitter: stop_int Data Shift Register (S1DAT) S1DAT contains the serial data to be transmitted or data which has just been received (see Table 51). The MSB (Bit 7) is transmitted or received first; that is, data shifted from right to left.
Table 49. Serial Status Register S1STA (DDH, Reset Value 00H)
Bit 7 GC Bit 6 STOP Bit 5 INTR Bit 4 TX_MODE Bit 3 BBUSY Bit 2 BLOST Bit 1 ACK_REP Bit 0 SLV
Table 50. S1STA Status Register Details
Bit 7 6 Symbol GC STOP General Call flag STOP flag. This bit is set when a STOP condition is received. Interrupt flag. This bit is set when a I2C interrupt is requested. Must be cleared with software. Transmission Mode flag. This bit is set when the I2C is a transmitter. Otherwise, this bit is reset. Bus Busy State flag. This bit is set when the bus is being used by another master. Otherwise, this bit is reset. Bus Lost flag. This bit is set when the master loses the bus contention. Otherwise, this bit is reset. Acknowledge response flag. This bit is set when the receiver transmits the not acknowledge signal. This bit is reset when the receiver transmits the acknowledge signal. Even if this bit is set, the STOP condition does not occur in the bus. (MASTER MODE) Slave Mode flag. This bit is set when the I2C plays role in the slave mode. Otherwise, this bit is reset. Function
5
INTR
4 3 2
TX_MODE BBUSY BLOST
1
ACK_REP
0
SLV
Table 51. Data Shift Register S1DAT (DEH, Reset Value 00H)
Bit 7 S1DAT7 Bit 6 S1DAT6 Bit 5 S1DAT5 Bit 4 S1DAT4 Bit 3 S1DAT3 Bit 2 S1DAT2 Bit 1 S1DAT1 Bit 0 S1DAT0
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Address Register (S1ADR) This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receive/transmitter (see Table 52). The Start/Stop Hold Time Detection and System Clock registers (Table 53 and Ta-
ble 54) are included in the I2C unit to specify the start/stop detection time to work with the large range of MCU frequency values supported. Table 55 is an example with a system clock of 40MHz.
Table 52. Address Register S1ADR (DFH, Reset Value 00H)
Bit 7 SLA6 Bit 6 SLA5 Bit 5 SLA4 Bit 4 SLA3 Bit 3 SLA2 Bit 2 SLA1 Bit 1 SLA0 Bit 0 -
Table 53. Start/Stop Hold Time Detection Register S1SETUP (DBH, Reset Value 00H)
Bit 7 Enable S1SETU Bit 6 - Bit 0 Bit 6 - 0 specify the number of sample clocks
Table 54. System Clock of 40MHz
S1SETUP Register Value No. of Sample Clock (fOSC = 25ns) 1EA 1EA 2EA 3EA ... 12EA 24EA ... 128EA 3000ns 300ns 600ns Fast Mode I2C Start/Stop Hold time specification Required Start/Stop Hold Time 25ns 25ns 50ns 75ns Note When Bit 7 (Enable bit) = 0, the number of sample clock is 1EA (ignore Bit 6 - Bit 0)
00H 80h 81h 82h ... 8Bh 97h ... FFh
Table 55. System Clock Setup Examples
System Clock 40MHz (fOSC -> 25ns) 30MHz (fOSC -> 33.3ns) 20MHz (fOSC -> 50ns) 8MHz (fOSC -> 125ns) S1SETUP Register Value 97h 91h 8Bh 84h No. of Sample Clock 24EA 18EA 12EA 5EA Required Start/Stop Hold Time 600ns 599ns 600ns 625ns
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SPI (SYNCHRONOUS PERIPHERAL INTERFACE) The SPI is a master interface that enables synchronous, serial communication with external slave peripherals. The SPI features full-duplex, three-wire synchronous transfers and programmable clock polarity (optional 4 wires). The SPI performs parallel-to-serial conversion on data written to a 8-bit wide Transmit data register (SPITDR) and serial-to-parallel conversion on received data, buffering a 8-bit wide Receive data register (SPIRDR). The SPI supports a subset of the SPI function, mainly the Master Mode with CPHA=1 Transfer Format. It will be able to interface a device that has a SPI Slave interface with the slave select being grounded or controlled by the SPI. The CPHA=1 Transfer Format requires that the first data bit is shifted out at the same time as the first SPICLK. The SPI has the following features: 1. Support Master Mode, 8 bit data size 2. Programmable Clock Polarity
3. 8-bit wide, double-buffered transmit and receive operation 4. Full-duplex - Both transmit and receive operate simultaneously with two wires 5. 3, or 4 wires external pins (see Figure 19): SPITxD - This pin is used to transmit data out of the SPI module. SPIRxD - This pin is used to receive data from slave mode. SPISEL - This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place. SPICLK - This pin is used to output the SPICLK clock 6. Programmable baud rate which can be modulated by SPICLKD register SPI Registers The SPI has seven registers for data transmit, receive, and control (see Table 56, page 51 through Table 60, page 52).
Figure 19. SPI Bus Interface
SPI
Tx[7:0] S PIS EL S PITDR
Tx_Shift_R eg 7 6543 2 10
S PITXD
Rx_Shift_R eg 7 6543 2 10
S PIR XD
Rx[7:0]
S PIR D R
S PIC LK
S C LKDIV fOS C
Clock Divider
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Table 56. SPI Registers
Register SPICON0 SPICON1 SPITDR SPIRDR SPICLKD SPISTAT SFR Offset D6H D7H D4H D5H D2H D3H Dir. RW RW W R RW R Control Register 0 Control Register 1 Transmit Data Register (data byte to be transmitted) Receive Data Register (store received data byte) Clock Divider Value Status Register Description Reset Value 00 00 00 00 04 02
Table 57. SPICON0 (Control Register 0) Details (D6H, Reset Value 00H)
BIT 7 6 SYMBOL - TE RW RW Reserved Transmitter Enable 0 = Transmitter is disabled 1 = Transmitter is enabled Receiver Enable 0 = Receiver is disabled 1 = Receiver is enabled SPI Enable 0 = SPI is disabled 1 = SPI is enabled Slave Selection 0 = Slave Select output is disabled 1 = Slave Select output is enabled on Port pin P1.7 (or P4.7) First LSB 0 = Transfer the most significant bit (MSB) first 1 = Transfer the least significant bit (LSB) first Sampling Polarity 0 = Sample transfer data at the falling edge of clock (SPICLK is '0' when idle) 1 = Sample transfer data at the rising edge of clock (SPICLK is '1' when idle) Reserved Definition
5
RE
RW
4
SPIEN
RW
3
SSEL
RW
2
FLSB
RW
1
SPO
RW
0
-
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Table 58. SPICON1 (Control Register 1) Details (D7H, Reset Value 00H)
BIT 7-4 3 SYMBOL - TEIE RW RW Reserved Transmission End Interrupt Enable 0 = SPI Transmission end Interrupt Disable 1 = SPI Transmission end Interrupt Enable Receive Overrun Interrupt Enable 0 = Receive Overrun Interrupt Disable 1 = Receive Overrun Interrupt Enable Transmission Interrupt Enable 0 = SPITDR empty interrupt Disable 1 = SPITDR Empty interrupt Enable Reception Interrupt Enable 0 = SPIRDR full interrupt Disable 1 = SPIRDR full interrupt Enable Definition
2
RORIE
RW
1
TIE
RW
0
RIE
RW
Table 59. SPICLKD (SPI Prescaler) Register (D2H, Reset Value 04H)
Bit 7 DIV128 Bit 6 DIV64 Bit 5 DIV32 Bit 4 DIV16 Bit 3 DIV8 Bit 2 DIV4 Bit 1 - Bit 0 -
Table 60. SPICLKD (SPI Prescaler) Details
BIT 7 6 5 4 3 2 1-0 SYMBOL DIV128 DIV64 DIV32 DIV16 DIV8 DIV4 Not Used RW RW RW RW RW RW RW Definition 0 = No division 1 = Divide fOSC clock by 128 T0 = No division 1 = Divide fOSC clock by 64 0 = No division 1 = Divide fOSC clock by 32 0 = No division 1 = Divide fOSC clock by 16 0 = No division 1 = Divide fOSC clock by 8 0 = No division 1 = Divide fOSC clock by 4
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The SPI serial clock frequency in Master Mode is the fOSC clock divided by the SPICLKD divisors. The bits in the SPICLKD register can be set to provide divisor values of multiple of 4: 4, 8, 12, 16, 20... to 252. Operation The SPI transmitter and receiver share the same clock but are independent, so full-duplex communication is possible. The transmitter and receiver are also double-buffered, so continuous transmitting or receiving (back-to-back transfer) is possible by reading or writing data while transmitting or receiving is in progress. SPI Configuration The SPI is reset by the CPU Reset. Control register SPICON0 needs to be programmed to decide several operation parameters. The SPO Bit determines clock polarity. When SPO is set to '0,' the data bit is placed on the communication line from one rising edge of serial clock to the next and is guaranteed valid at the fall of serial clock. When SPO is set to '1,' the data bit is placed on the communication line from one falling edge of serial clock to the next and is guaranteed valid at the rise of serial clock. The FLSB Bit determines the format of 8-bit serial data transfer. When FLSB is '0,' the 8-bit data is transferred in order from MSB (first) to LSB (last). When FLSB is '1,' the data is transferred in order from LSB (first) to MSB (last). The bit rate requires the programming of the clock divider register SPICLKD. The value of SPICLKD divides the fOSC clock to provide the serial transfer clock output -SPICLK. The SPICON1 and SPICON0 have SPI Transmitter Enable (TE) and Receiver Enable (RE) and Interrupt Enable Bits (TEIE, RORIE,TIE, RIE). If TE is disabled, both transmitting and receiving are disabled because SPICLK is forced to LOW (SPO=0) or HIGH (SPO=1).
Table 61. SPISTAT (Status) Register (D3H, Reset Value 02H)
Bit 7 - Bit 6 - Bit 5 - Bit 4 BUSY Bit 3 TEISF Bit 2 RORISF Bit 1 TISF Bit 0 RISF
Table 62. SPISTAT (Status) Register Details
BIT 7-5 4 SYMBOL Reserved BUSY R SPI Busy 0 = Tx/Rx is completed 1 = Tx/Rx is on going Transmission End Interrupt Source flag 0 = Reset when users read this register 1 = Set when transmission end occurs Receive Overrun Interrupt Source flag 0 = Reset when user reads this register 1 = Set when Rx Overrun occurs Transfer Interrupt Source flag 0 = Reset when SPITDR is full (when the SPITDR is written) 1 = Set when SPITDR is empty Receive Interrupt Source flag 0 = Reset when SPIRDR is empty (when the SPITDR is read) 1 = Set when SPIRDR is full RW Definition
3
TEISF
R
2
RORISF
R
1
TISF
R
0
RISF
R
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Slave Select Output The SPI can be operated as a SPI bus in Master Mode. The Slave Select (SPISEL) line in the SPI bus is assigned to port pin P1.7 (or P4.7). When the SSEL Bit is set in the Control Register, the SPI drives the SPISEL line low to select the slave device before data transmission. The rising edge of SPISEL occurs after the last bit is shifted out. Transmit operation. In transmitting serial data, the SPI operates as follows: 1. The initial sequence would be: - CPU writes the byte to SPITDR, - CPU sets SPIEN = 1, TIE = 1, - CPU sets TE = 1 to enable transmit, - SPI loads TSR with data from TDR, and - SPI sets TISF and interrupts the CPU to write the second byte. 2. In the ISR (Interrupt Service Routine) for SPI, the CPU writes new data on SPITDR. This update will automatically clear TISF. 3. If TISF is cleared (i.e., SPITDR has a valid data) and the TSR (Transmit Shift Register) is ready Figure 20. SPI Transmit Operation Example
1 frame SPICLK (SPO=0) SPICLK (SPO=1) SPITXD Bit0 Bit1 Bit7 Bit0 Bit1
to load new data (e.g., the last bit (8th bit) of the TSR is being sent, or the TSR is empty), the SPI will load the TSR with data on SPITDR and set TISF to '1' (i.e., request CPU to fill SPITDR). 4. The SPI checks the TISF flag when it outputs the last bit (8th bit) of the eight-bit serial transmission data. - If the TISF flag is '0,' the SPI loads data from SPITDR into the TSR and begins serial transmission of the next 8-bit frame (continuous transfer). - If the TISF is '1,' the SPI sets the TEISF flag to '1' in SPISTAT, and if the TEIE Bit is set to '1' in SPICON1, a Transmit End Interrupt is requested at this time. So, the TISF Bit must be '0' before the last bit is transmitted to perform continuous transfer. After transmitting the last bit, the SPI holds the SPITxD pin in the last bit state. 5. After the end of serial transmission, the SPICLK pin is held in a constant state.
Bit7
TISF
TEISF
BUSY
SPISEL
SPIINTR SPITDR Empty interrupt requested Interrupt handler write data in TDR SPITDR Empty interrupt requested Transmit End interrupt requested
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Receive Operation In receiving serial data, the SPI operates as follows: 1. The SPI generates serial clock and synchronizes internally. 2. Received data is stored in the RSR (Receive Shift Register) in order from MSB to LSB (FLSB = 0) or from LSB to MSB (FLSB = 1). After receiving the data, the SPI checks to see if the RIS flag is '0' or not. If this check passes, the received data in the RSR is stored in SPIRDR and the RIS flag is set to 1.
When the check fails (i.e., the RIS flag is '1' or the last received data in SPIRDR is not read until the 8th bit of currently received data is received in the RSR), the RORIS flag is set to '1' and received data in the RSR is lost. When the RORIS flag is set to '1' and the RORIE Bit is set to '1' at SPICON1, the subsequent transmit and receive operations are disabled. 3. If the RIE Bit in SPICON1 is set to '1' and the RIS flag is set to '1,' the SPIRDR Full Interrupt is requested. If the RORIE Bit in SPICON1 is set to '1' and the RORIS flag is set to '1,' the Receive Overrun Interrupt is requested.
Figure 21. SPI Receive Operation Example
1 frame SPICLK (SPO=0) SPICLK (SPO=1) SPIRXD Bit7 Bit0 Bit1 Bit7 Bit0 Bit1
Bit7
RISF
RORIS
BUSY
SPIINTR SPIRDR Full interrupt requested Interrupt handler read data in SPIRDR SPIRDR Full interrupt requested Transmit End interrupt requested
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ANALOG-TO-DIGITAL CONVERTOR (ADC) The ADC unit in the PSD33XX is a SAR type ADC with a SAR register, an auto-zero comparator and three internal DACs. The unit has 8 input channels with 10-bit resolution. The A/D converter has its own VREF input (80-pin package only), which specifies the voltage reference for the A/D operations. The analog to digital converter (A/D) allows conversion of an analog input to a corresponding 10-bit digital value. The A/D module has eight analog inputs (P1.0 through P1.7) to an 8x1 multiplexor. One ADC channel is selected by the bits in the configuration register. The converter generates a 10-bits result via successive approximation. The analog supply voltage is connected to the VREF input, which powers the resistance ladder in the A/D module. The A/D module has 3 registers, the control register ACON, the A/D result register ADAT0, and the second A/D result register ADAT1. The ADAT0 register stores Bits 0.. 7 of the converter output, Bits 8.. 9 are stored in Bits 0..1 of the ADAT1 register. The ACON register controls the operation of the A/D converter module. Three of the bits in the ACON register select the analog channel inputs, and the remaining bits control the converter operation. ADC channel pin input is enabled by setting the corresponding bit in the P1SFS0 and P1SFS1 registers to '1' and the channel select bits in the ACON register. The ADC reference clock (ADCCLK) is generated from fOSC divided by the divider in the ADCPS regFigure 22. 10-Bit ADC
AVREF AVREF
ister. The ADC operates within a range of 2 to 16MHz, with typical ADCCLK frequency at 8MHz. The conversion time is 4s typical at 8MHz. The processing of conversion starts when the Start Bit ADST is set to '1.' After one cycle, it is cleared by hardware. The ADC is monotonic with no missing codes. Measurement is by continuous conversion of the analog input. The ADAT register contains the results of the A/D conversion. When conversion is complete, the result is loaded into the ADAT. The A/D Conversion Status Bit ADSF is set to '1.' The block diagram of the A/D module is shown in Figure 22. The A/D status bit ADSF is set automatically when A/D conversion is completed and cleared when A/D conversion is in process. In addition, the ADC unit sets the interrupt flag in the ACON register after a conversion is complete (if AINTEN is set to '1'). The ADC interrupts the CPU when the enable bit AINTEN is set. Port 1 ADC Channel Selects The P1SFS0 and P1SFS1 Registers control the selection of the Port 1 pin functions. When the P1SFS0 Bit is '0,' the pin functions as a GPIO. When bits are set to '1,' the pins are configured as alternate functions. A new P1SFS1 Register selects which of the alternate functions is enabled. The ADC channel is enabled when the bit in P1SFS1 is set to '1.' Note: In the 52-pin package, there is no individual VREF pin.
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 SELECT CONTROL ADC OUT - 10 BITS 10-BIT SAR ADC ANALOG MUX
ACON REG
ADAT1 REG
ADAT 0 REG
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Table 63. ACON Register (97H, Reset Value 00H)
Bit 7 AINTF Bit 6 AINTEN Bit 5 ADEN Bit 4 ADS2 Bit 3 ADS1 Bit 2 ADS0 Bit 1 ADST Bit 0 ADSF
Table 64. ACON Register Details
Bit Symbol Function ADC Interrupt flag. This bit must be cleared with software. 0 = No interrupt request 1 = The AINTF flag is set when ADSF goes from '0' to '1.' Interrupts CPU when both AINTF and AINTEN are set to '1.' ADC Interrupt Enable 0 = ADC interrupt is disabled 1 = ADC interrupt is enabled ADC Enable Bit 0 = ADC shut off and consumes no operating current 1 = Enable ADC. ADC must be enabled before setting the ADST Bit. Analog channel Select 000 Select channel 0 (P1.0) 001 Select channel 0 (P1.1) 010 Select channel 0 (P1.2) 011 Select channel 0 (P1.3) 101 Select channel 0 (P1.5) 110 Select channel 0 (P1.6) 111 Select channel 0 (P1.7) ADC Start Bit 0 = Force to zero 1 = Start and ADC, then after one cycle, the bit is cleared to '0.' ADC Status Bit 0 = ADC conversion is not completed 1 = ADC conversion is completed. The bit can also be cleared with software.
7
AINTF
6
AINTEN
5
ADEN
4.. 2
ADS2.. 0
1
ADST
0
ADSF
Table 65. ADCPS Register Details (94H, Reset Value 00H)
Bit 7:4 3 Symbol - ADCCE Reserved ADC Conversion Reference Clock Enable 0 = ADC reference clock is disabled (default) 1 = ADC reference clock is enabled ADC Reference Clock PreScaler fACLK = fOSC/2ADCPS[2:0] Example: for fOSC = 40MHz and ADCPS[2:0] = 2, the fACLK = 40/22 = 10MHz. fACLK frequency range must be 2-16MHz. Function
2:0
ADCPS[2:0]
Table 66. ADAT0 Register (95H, Reset Value 00H)
Bit 7:0 Symbol - Store ADC output, Bit 7 - 0 Function
Table 67. ADAT1 Register (96H, Reset Value 00H)
Bit 7:2 1.. 0 Symbol - - Reserved Store ADC output, Bit 9, 8 Function
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PROGRAMMABLE COUNTER ARRAY (PCA) WITH There are two Programmable Counter Array blocks (PCA0 and PCA1) in the PSD33XX. A PCA block consists of a 16-bit up-counter, which is shared by three TCM (Timer Counter Module). A TCM can be programmed to perform one of the following four functions: 1. Capture Mode: capture counter values by external input signals 2. Timer Mode 3. Toggle Output Mode 4. PWM Mode: fixed frequency (8-bit or 16-bit), programmable frequency (8-bit only) PCA Block The 16-bit Up-Counter in the PCA block is a freerunning counter (except in PWM Mode with programmable frequency). The Counter has a choice Figure 23. PCA0 Block Diagram
PCA0CLK TIMER0 OVERFLOW P4.3/ECI EOVFI CLKSEL1 CLKSEL0 TCM0 P4.0/CEX0 16-bit up Timer/Counter PCACH0 8-bit PCACL0 8-bit OVF0 INT
PWM of clock input: from an external pin, Timer 0 Overflow, or PCA Clock. A PCA block has 3 Timer Counter Modules (TCM) which share the 16-bit Counter output. The TCM can be configured to capture or compare counter value, generate a toggling output, or PWM functions. Except for the PWM function, the other TCM functions can generate an interrupt when an event occurs. Every TCM is connected to a port pin in Port 4; the TCM pin can be configured as an event input, a PWMs, a Toggle Output, or as External Clock Input. The pins are general I/O pins when not assigned to the TCM. The TCM operation is configured by Control registers and Capture/Compare registers. Table 68, page 59 lists the SFR registers in the PCA blocks.
EN_ALL EN_PCA PCAIDLE IDLE MODE (From CPU)
TCM1
P4.1/CEX1
TCM2
P4.2/CEX2
PWM FREQ COMPARE CLEAR COUNTER
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Table 68. PCA0 and PCA1 Registers
SFR Address PCA0 A2 A3 A4 PCA1 Register Name RW PCA0 PCACL0 PCACH0 PCACON0 PCA1 PCACL1 PCACH1 PCACON1 RW RW RW The low 8 bits of PCA 16-bit counter. The high 8 bits of PCA 16-bit counter. Control Register
s Enable PCA, Timer Overflow flag , PCA
Register Function
Idle Mode, and Select clock source. A5 A9, AA, AB AC AD AF B1 B2 B3 B4 BD, BE, BF C1 C2 C3 C4 C5 C6 C7 PCASTA TCMMODE0 TCMMODE1 TCMMODE2 CAPCOML0 CAPCOMH0 CAPCOML1 CAPCOMH1 CAPCOML2 CAPCOMH2 PWMF0 N/A TCMMODE3 TCMMODE4 TCMMODE5 CAPCOML3 CAPCOMH3 CAPCOML4 CAPCOMH4 CAPCOML5 CAPCOMH5 PWMF1 RW Status Register, Interrupt Status flags
s Common for both PCA Block 0 and 1.
TCM Mode RW
s Capture, Compare, and Toggle Enable
Interrupts
s PWM Mode Select.
RW RW RW
Capture/Compare registers of TCM0 Capture/Compare registers of TCM1 Capture/Compare registers of TCM2 The 8-bit register to program the PWM frequency. This register is used for programmable, 8-bit PWM Mode only.
RW
Operation of TCM Modes Each of the TCM in a PCA block supports four modes of operation. However, an exception is when the TCM is configured in PWM Mode with programmable frequency. In this mode, all TCM in a PCA block must be configured in the same mode or left to be not used. Capture Mode The CAPCOM registers in the TCM are loaded with the counter values when an external pin input changes state. The user can configure the counter value to be loaded by positive edge, negative edge or any transition of the input signal. At loading, the TCM can generate an interrupt if it is enabled. Timer Mode The TCM modules can be configured as software timers by enable the comparator. The user writes a value to the CAPCOM registers, which is then compared with the 16-bit counter. If there is a match, an interrupt can be generated to CPU.
Toggle Mode In this mode, the user writes a value to the TCM's CAPCOM registers and enables the comparator. When there is a match with the Counter output, the output of the TCM pin toggles. This mode is a simple extension of the Timer Mode. PWM Mode - (X8), Fixed Frequency In this mode, one or all the TCM's can be configured to have a fixed frequency PWM output on the port pins. The PWM frequency depends on when the low byte of the Counter overflows (module 256). The duty cycle of each TCM module can be specified in the CAPCOMHn register. When the PCA_Counter_L value is equal to or greater than the value in CAPCOMHn, the PWM output is switched to a high state. When the PCA_Counter_L Register overflows, the content in CAPCOMHn is loaded to CAPCOMLn and a new PWM pulse starts.
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Figure 24. Timer Mode
CAPCOMHn
8 ENABLE
CAPCOMLn
8
INTFn
PCASTA
MATCH_TIMER INTR
16-bit COMPARATOR
8 8
MATCH
PCACHm
PCACLm
16-bit up Timer/Counter
TCMMODEn
EINTF
E_COMP CAP_PE 0
CAP_NE 0
MATCH TOGGLE 0 RESET WRITE to CAPCOMHn 1
PWM1 0
PWM0 0
C
D
EN_FLAG
0 WRITE to CAPCOMLn
AI07858
Note: m = 0: n = 0, 1, or 2 m = 1: n = 3, 4, or 5
Figure 25. PWM Mode - (X8), Fixed Frequency
CAPCOMHn
8
CAPCOMLn
ENABLE
8-bit COMPARATORn
8
MATCH
S
SET
Q
CEXn
OVERFLOW
PCACLm
R
CLR
Q
TCMMODEn
EINTF 0
E_COMP CAP_PE 0
CAP_NE 0
MATCH TOGGLE 0 0
PWM1
PWM0
AI07859
Note: m = 0: n = 0, 1, or 2 m = 1: n = 3, 4, or 5
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PWM Mode - (X8), Programmable Frequency In this mode, the PWM frequency is not determined by the overflow of the low byte of the Counter. Instead, the frequency is determined by the PWMFm register. The user can load a value in the PWMFm register, which is then compared to the low byte of the Counter. If there is a match, the Counter is cleared and the Load registers (PWMFm, CAPCOMHn) are re-loaded for the next PWM pulse. There is only one PWMFm Register which serves all 3 TCM in a PCA block.
If one of the TCM modules is operating in this mode, the other modules in the PCA must be configured to the same mode or left not to be used. The duty cycle of the PWM can be specified in the CAPCOMHn register as in the PWM with fixed frequency mode. Different TCM modules can have their own duty cycle. Note: The value in the Frequency register (PWMFm) must be larger than the duty cycle register (CAPCOM).
Figure 26. PWM Mode - (X8) Programmable Frequency
PWM FREQ COMPARE
PWMFm
8 PWMFm = PCACLm
CAPCOMHn
8
PCACHm
CAPCOMLn
MATCH ENABLE
8-bit COMPARATORm
ENABLE
8-bit COMPARATORn
S
SET
Q
CEXn
8
R CLR
Q
CLR
PCACLm
TCMMODEn
EINTF 0
E_COMP CAP_PE 0
CAP_NE 0
MATCH TOGGLE 0 0
PWM1
PWM0
AI07860
Note: m = 0: n = 0, 1, or 2 m = 1: n = 3, 4, or 5
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PWM Mode - Fixed Frequency, 16-bit The operation of the 16-bit PWM is the same as the 8-bit PWM with fixed frequency. In this mode, one or all the TCM can be configured to have a fixed frequency PWM output on the port pins. The PWM frequency is depending on the clock input frequency to the 16-bit Counter. The duty cycle of each TCM module can be specified in the CAPCOMHn and CAPCOMLn registers. When the 16 bit PCA_Counter is equal or greater than the values in registers CAPCOMHn and CAPCOMLn, the PWM output is switched to a high state. When the PCA_Counter overflows, CEXn is asserted low. Writing to Capture/Compare Registers When writing a 16-bit value to the PCA0 Capture/ Compare registers, the low byte should always be written first. Writing to CAPCOMLn clears the
E_COMP bit to '0'; writing to CAPCOMHn sets E_COMP to '1' the largest duty cycle is 100% (CAPCOMHn CAPCOMLn = 0x0000), and the smallest duty cycle is 0.0015% (CAPCOMHn CAPCOMLn = 0xFFFF). A 0% duty cycle may be generated by clearing the E_COMP bit to `0'. Control Register Bit Definition Each PCA has its own PCA_CONFIGn, and each module within the PCA block has its own TCM_Mode Register which defines the operation of that module (see Table 69 through Table 71). There is one PCA_STATUS Register that covers both PCA0 and PCA1 (see Table 72, page 62 and Table 73, page 63).
Table 69. PCA0 Control Register PCACON0 (0A4H, Reset Value 00H)
Bit 7 EN-ALL Bit 6 EN_PCA Bit 5 EOVFI Bit 4 PCAIDLE Bit 3 - Bit 2 - Bit 1 Bit 0 CLK_SEL[1:0]
Table 70. PCA1 Control Register PCACON0 (0BCH, Reset Value 00H)
Bit 7 EN-ALL Bit 6 EN_PCA Bit 5 EOVFI Bit 4 PCAIDLE Bit 3 - Bit 2 - Bit 1 Bit 0 CLK_SEL[1:0]
Table 71. PCA0, PCA1 Register Details
Bit Symbol Function 0 = No impact on TCM modules 1 = Enable both PCA counters simultaneously (override the EN_PCA Bits) This bit is to synchronize the two 16-bit counters in the PCA. For customers who want 5 PWM, for example, this bit can synchronize all of the PWM outputs. 0 = PCA counter is disabled 1 = PCA counter is enabled EN_PCA Counter Run Control Bit. Set with software to turn the PCA counter on. Must be cleared with software to turn the PCA counter off. 1 = Enable Counter Overflow Interrupt if overflow flag (OVF) is set 0 = PCA operates when CPU is in Idle Mode 1 = PCA stops running when CPU is in Idle Mode Reserved 00 Select Prescaler clock as Counter clock 01 Select Timer 0 Overflow 10 Select External Clock pin (P4.3 for PCA0, P4.7 for PCA1) (MAX clock rate = fOSC/4)
7
EN-ALL
6
EN_PCA
5 4 3-2 1-0
EOVFI PCAIDLE - CLK_SEL [1:0]
Table 72. PCA Status Register PCASTA (0A5H, Reset Value 00H)
Bit 7 OVF1 Bit 6 INTF5 Bit 5 INTF4 Bit 4 INTF3 Bit 3 OVF0 Bit 2 INTF2 Bit 1 INTF1 Bit 0 INTF0
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Table 73. PCA Status Register PCASTA Details
Bit Symbol Function PCA1 Counter OverFlow flag. Set by hardware when the counter rolls over. OVF1 flags an interrupt if Bit EOVFI in PCACON1 is set. OVF1 may be set with either hardware or software but can only be cleared with software. TCM5 Interrupt flag. Set by hardware when a match or capture event occurs. Must be clear with software. TCM4 Interrupt flag. Set by hardware when a match or capture event occurs. Must be clear with software. TCM3 Interrupt flag. Set by hardware when a match or capture event occurs. Must be clear with software. PCA0 Counter OverFlow flag. Set by hardware when the counter rolls over. OVF0 flags an interrupt if Bit EOVFI in PCACON0 is set. OVF1 may be set with either hardware or software but can only be cleared with software. TCM2 Interrupt flag. Set by hardware when a match or capture event occurs. Must be clear with software. TCM1 Interrupt flag. Set by hardware when a match or capture event occurs. Must be clear with software. TCM0 Interrupt flag. Set by hardware when a match or capture event occurs. Must be clear with software.
7
OFV1
6
INTF5
5
INTF4
4
INTF3
3
OVF0
2
INTF2
1
INTF1
0
INTF0
TCM Interrupts There are 8 TCM interrupts: 6 match or capture interrupts and two counter overflow interrupts. The 8 interrupts are "ORed" as one PCA interrupt to the CPU. By the nature of PCA application, it is unlikely that many of the interrupts occur simultaneous-
ly. If they do, the CPU has to read the interrupt flags and determine which one to serve. The software has to clear the interrupt flag in the Status Register after serving the interrupt.
Table 74. TCMMODE0 - TCMMODE5 (6 Registers, Reset Value 00H)
Bit 7 EINTF Bit 6 E_COMP Bit 5 CAP_PE Bit 4 CAP_NE Bit 3 MATCH Bit 2 TOGGLE Bit 1 PWM[1:0] Bit 0
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Table 75. TCMMODE0 - TCMMODE5 Register Details
e 7 6 5 4 3 2 Symbol EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE Function 1 - Enable the interrupt flags (INTF) in the Status Register to generate an interrupt. 1 - Enable the comparator when set 1 - Enable Capture Mode, a positive edge on the CEXn pin. 1 - Enable Capture Mode, a negative edge on the CEXn pin. 1 - A match from the comparator sets the INTF bits in the Status Register. 1 - A match on the comparator results in a toggling output on CEXn pin. 01 Enable PWM Mode (x8), fixed frequency. Enable the CEXn pin as a PWM output. 10 Enable PWM Mode (x8) with programmable frequency. Enable the CEXn pin as a PWM output. 11 Enable PWM Mode (x16), fixed frequency. Enable the CEXn pin as a PWM output.
1-0
PWM[1:0]
Table 76. TCMMODE Register Configurations
EINTF 0 0 0 0 X X X X X E_COMP CAP_PE CAP_NE MATCH TOGGLE 0 1 1 1 1 1 X X X 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 PWM1 0 0 1 1 0 0 0 0 0 PWM0 0 1 0 1 0 0 0 0 0 TCM FUNCTION No operation (reset value) 8-bit PWM, fixed frequency 8-bit PWM, programmable frequency 16-bit PWM, fixed frequency 16-bit toggle 16-bit Software Timer 16-bit capture, negative trigger 16-bit capture, positive trigger 16-bit capture, transition trigger
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PSD MODULE s The PSD Module provides configurable Program and Data memories to the Turbo 8032 MCU Module. In addition, it has its own set of I/ O ports and a PLD with 16 macrocells for general logic implementation. s Ports A,B,C, and D are general purpose programmable I/O ports that have a port architecture which is different from the I/O ports in the MCU Module. s The PSD Module communicates with the MCU Module through the internal address, data bus (A0-A15, D0-D7) and control signals (RD, WR, PSEN, ALE, RESET). The user defines the Decoding PLD in the PSDsoft Development Tool and can map the resources in the PSD Module to any program or data address space. Figure 27, page 66 shows the functional blocks in the PSD Module. Functional Overview s 64K, 128K, or 256K bytes Flash memory. This is the main Flash memory. It is divided into equally-sized blocks that can be accessed with user-specified addresses. s Secondary 16K or 32K bytes Flash boot memory. It is divided into equally-sized blocks that can be accessed with user-specified addresses. This secondary memory brings the ability to execute code and update the main Flash concurrently. s 2K, 8K, or 32K bytes SRAM. The SRAM's contents can be protected from a power failure by connecting an external battery. s CPLD with 16 Output Micro Cells (OMCs} and 20 Input Micro Cells (IMCs). The CPLD may be used to efficiently implement a variety of logic functions for internal and external control.
s s
Examples include state machines, loadable shift registers, and loadable counters. Decode PLD (DPLD) that decodes address for selection of memory blocks in the PSD Module. Configurable I/O ports (Port A,B,C and D) that can be used for the following functions: - MCU I/Os - PLD I/Os - Latched MCU address output - Special function I/Os. - I/O ports may be configured as open-drain outputs.
s
s
s
s
Built-in JTAG compliant serial port allows fullchip In-System Programmability (ISP). With it, you can program a blank device or reprogram a device in the factory or the field. Internal page register that can be used to expand the 8032 MCU Module address space by a factor of 256. Internal programmable Power Management Unit (PMU) that supports a low-power mode called Power-down Mode. The PMU can automatically detect a lack of the 8032 CPU core activity and put the PSD Module into Power-down Mode. Erase/WRITE cycles: - Flash memory - 100,000 minimum - PLD - 1,000 minimum - Data Retention: 15 year minimum (for Main Flash memory, Boot, PLD and Configuration bits)
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ADDRESS/DATA/CONTROL BUS PLD INPUT BUS PAGE REGISTER EMBEDDED ALGORITHM PRIMARY FLASH MEMORY 8 POWER MANGMT UNIT VSTDBY (PC2) BUS Interface FLASH DECODE PLD (DPLD) 73 SECTOR SELECTS SRAM SELECT PERIP I/O MODE SELECTS CSIOP BUS Interface 73 FLASH ISP CPLD (CPLD) RUNTIME CONTROL AND I/O REGISTERS 2 EXT CS TO PORT D 16 OUTPUT MACROCELLS PORT A ,B & C 20 INPUT MACROCELLS CLKIN PORT A ,B & C PROG. PORT GLOBAL CONFIG. & SECURITY CLKIN MACROCELL FEEDBACK OR PORT INPUT PORT C PROG. PORT PORT B PORT A BATTERY BACKUP SRAM SECTOR SELECTS SECONDARY NON-VOLATILE MEMORY (BOOT OR DATA) PROG. PORT PA0 - PA7 PB0 - PB7 PC0 - PC7 PROG. PORT CLKIN (PD1) PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PORT D PD1 - PD2
PSD33XX
8032 Bus
Figure 27. PSD Module Block Diagram
WR_, RD_, PSEN_, ALE, RESET_, A0-A15
D0 - D7
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PSD33XX
PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET Table 77 shows the offset addresses to the PSD PSD Module registers. Table 79, page 69 provides Module registers relative to the CSIOP base adbrief descriptions of the registers in CSIOP space. dress. The CSIOP space is the 256 bytes of adThe following section gives a more detailed dedress that is allocated by the user to the internal scription. Table 77. Register Address Offset
Register Name Data In Control Data Out Direction Drive Select Input Macrocell Enable Out Output Macrocells AB Output Macrocells BC Mask Macrocells AB Mask Macrocells BC Primary Flash Protection Secondary Flash memory Protection PMMR0 PMMR2 Page VM
Note: 1. Other registers that are not part of the I/O ports.
Port A 00 02 04 06 08 0A 0C 20
Port B 01 03 05 07 09 0B 0D 20 21
Port C 10
Port D 11
Other(1)
Description Reads Port pin as input, MCU I/O Input Mode Selects mode between MCU I/O or Address Out
12 14 16 18 1A
13 15 17
Stores data for output to Port pins, MCU I/O Output Mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Reads Input Macrocells
1B
Reads the status of the output enable to the I/O Port driver READ - reads output of macrocells AB WRITE - loads macrocell flip-flops
21
READ - reads output of macrocells BC WRITE - loads macrocell flip-flops Blocks writing to the Output Macrocells AB
22
22 23 23 C0 C2 B0 B4 E0 E2
Blocks writing to the Output Macrocells BC Read-only - Primary Flash Sector Protection Read-only - PSD Module Security and Secondary Flash memory Sector Protection Power Management Register 0 Power Management Register 2 Page Register Places PSD Module memory areas in Program and/or Data space on an individual basis.
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PSD MODULE DETAILED OPERATION As shown in Figure 27, page 66, the PSD Module consists of five major types of functional blocks: s Memory Block
s s s s
PLD Blocks I/O Ports Power Management Unit (PMU) JTAG Interface
The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable.
MEMORY BLOCKS The PSD Module has the following memory blocks (see Table 78): - Primary Flash memory - Secondary Flash memory - SRAM The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are userdefined in PSDsoft Express. Primary Flash Memory and Secondary Flash memory Description The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors. Each sector of either memory block can be separately protected from Program and Erase cycles. Flash memory may be erased on a sector-by-sector basis. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading.
During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy (PC3). This pin is set up using PSDsoft Express Configuration. Memory Block Select Signals The DPLD generates the Select signals for all the internal memory blocks (see the section entitled "PLDs," page 78). Each of the sectors of the primary Flash memory has a Select signal (FS0-FS7) which can contain up to three product terms. Each of the four sectors of the secondary Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in Program or Data space. Flash Memory Instructions The Flash memory instructions are detailed in Table 79. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cycle. Address signals A15-A12 are Don't Care during the instruction WRITE cycles. However, the appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be selected. The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of Sector Select (FS0-FS7) is High, and the secondary Flash memory is selected if any one of Sector Select (CSBOOT0CSBOOT3) is High.
Table 78. PSD33XX Memory Configuration
Main Flash Device Flash Size PSD3312 PSD3333 PSD3334 PSD3354 64KB 128KB 256KB 256KB Sector Size 16KB 16KB 32KB 32KB # of Sectors (Sector Select Signal) 4 (FS0-3) 8 (FS0-7) 8 (FS0-7) 8 (FS0-7) Flash Size 16KB 32KB 32KB 32KB Secondary Flash Sector Size 8KB 8KB 8KB 8KB # of Sectors (Sector Select Signal) 2 (CSBOOT0-1) 4 (CSBOOT0-3) 4 (CSBOOT0-3) 4 (CSBOOT0-3) SRAM Size 2KB 8KB 32KB 32KB
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Table 79. Instructions
Instruction READ(5) READ Sector Protection(6,8,13) Program a Flash Byte(13) Flash Sector Erase(7,13) Flash Bulk Erase(13) Suspend Sector Erase(11) Resume Sector Erase(12) RESET(6) Unlock Bypass Unlock Bypass Program(9) Unlock Bypass Reset(10) FS0-FS7 or CSBOOT0CSBOOT3 1 1 1 1 1 1 1 1 1 1 1 Cycle 1 "Read" RD @ RA AAh@ X555h AAh@ X555h AAh@ X555h AAh@ X555h B0h@ XXXXh 30h@ XXXXh F0h@ XXXXh AAh@ X555h A0h@ XXXXh 90h@ XXXXh 55h@ XAAAh PD@ PA 00h@ XXXXh 20h@ X555h 55h@ XAAAh 55h@ XAAAh 55h@ XAAAh 55h@ XAAAh 90h@ X555h A0h@ X555h 80h@ X555h 80h@ X555h Read status @ XX02h PD@ PA AAh@ X555h AAh@ X555h 55h@ XAAAh 55h@ XAAAh 30h@ SA 10h@ X555h 30h7@ next SA Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
Note: 1. All bus cycles are WRITE bus cycles, except the ones with the "Read" label 2. All values are in hexadecimal: X = Don't care. Addresses of the form XXXXh, in this table, must be even addresses RA = Address of the memory location to be read RD = Data READ from location RA during the READ cycle PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR, CNTL0). PA is an even address for PSD in Word Programming Mode. PD = Data word to be programmed at location PA. Data is latched on the rising edge of WRITE Strobe (WR , CNTL0) SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be erased, or verified, must be Active (High). 3. Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) signals are active High, and are defined in PSDsoft Express. 4. Only address Bits A11-A0 are used in instruction decoding. 5. No Unlock or instruction cycles are required when the device is in the READ Mode 6. The RESET instruction is required to return to the READ Mode after reading the Sector Protection Status, or if the Error Flag Bit (DQ5/DQ13) goes High. 7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80s. 8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0)=(1,0) 9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass Mode. 11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase Mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle. 12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase Mode. 13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must retrieve, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory.
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READ Flash Memory After power-up, the MCU may read the primary Flash memory or the secondary Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read sector protection and the Erase/Program status bits. Reading the Erase/Program Status Bits. The Flash memory provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 80, page 71. The status bits can be read as many times as needed. For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See the section entitled "Programming Flash Memory, page 71," for details. Data Polling Flag (DQ7). When erasing or programming in Flash memory, the Data Polling Flag Bit (DQ7) outputs the complement of the bit being entered for programming/writing on the DQ7 Bit. Once the Program instruction or the WRITE operation is completed, the true logic value is read on the Data Polling Flag Bit (DQ7) (in a READ operation). s Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. s During an Erase cycle, the Data Polling Flag Bit (DQ7) outputs a '0.' After completion of the cycle, the Data Polling Flag Bit (DQ7) outputs the last bit programmed (it is a '1' after erasing). s If the byte to be programmed is in a protected Flash memory sector, the instruction is ignored. s If all the Flash memory sectors to be erased are protected, the Data Polling Flag Bit (DQ7) is reset to '0' for about 100s, and then returns to the previous addressed byte. No erasure is performed.
Toggle Flag (DQ6). The Flash memory offers another way for determining when the Program cycle is completed. During the internal WRITE operation and when either the FS0-FS7 or CSBOOT0CSBOOT3 is true, the Toggle Flag Bit (DQ6) toggles from '0' to '1' and '1' to '0' on subsequent attempts to read any byte of the memory. When the internal cycle is complete, the toggling stops and the data READ on the Data Bus D0-D7 is the addressed memory byte. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive Reads yield the same output data. s The Toggle Flag Bit (DQ6) is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). s If the byte to be programmed belongs to a protected Flash memory sector, the instruction is ignored. s If all the Flash memory sectors selected for erasure are protected, the Toggle Flag Bit (DQ6) toggles to '0' for about 100s and then returns to the previous addressed byte. Error Flag (DQ5). During a normal Program or Erase cycle, the Error Flag Bit (DQ5) is to '0.' This bit is set to '1' when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Error Flag Bit (DQ5) indicates the attempt to program a Flash memory bit from the programmed state, '0', to the erased state, '1,' which is not valid. The Error Flag Bit (DQ5) may also indicate a Time-out condition while attempting to program a byte. In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash memory sector in which the error occurred or to which the programmed byte belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag Bit (DQ5) is reset after a Reset Flash instruction. Erase Time-out Flag (DQ3). The Erase Timeout Flag Bit (DQ3) reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase Time-out Flag Bit (DQ3) is reset to '0' after a Sector Erase cycle for a time period of 100s + 20% unless an additional Sector Erase instruction is decoded. After this time period, or when the additional Sector Erase instruction is decoded, the Erase Time-out Flag Bit (DQ3) is set to '1.'
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Table 80. Status Bit
Functional Block FS0-FS7/ CSBOOT0CSBOOT3 VIH(3) DQ7(2) DQ6(2) DQ5(2) DQ4(1,2) DQ3(2) DQ2(1,2) DQ1(1,2) Erase Timeout DQ0(1,2)
Flash Memory
Data Polling
Toggle Flag
Error Flag
X
X
X
X
Note: 1. X = Not guaranteed value, can be read either '1' or '0.' 2. DQ7-DQ0 represent the Data Bus bits, D7-D0. 3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.
Programming Flash Memory Flash memory must be erased prior to being programmed. A byte of Flash memory is erased to all '1s' (FFh), and is programmed by setting selected bits to '0.' The MCU may erase Flash memory all at once or by-sector, but not byte-by-byte. However, the MCU may program Flash memory byte-bybyte. The primary and secondary Flash memories require the MCU to send an instruction to program a byte or to erase sectors (see Table 79, page 69).
Once the MCU issues a Flash memory Program or Erase instruction, it must check for the status bits for completion. The embedded algorithms that are invoked support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (PC3).
Figure 28. Data Polling Flowchart
START
Figure 29. Data Toggle Flowchart
START
READ DQ5 & DQ7 at VALID ADDRESS
READ DQ5 & DQ6
DQ7 = DATA NO NO
YES
DQ6 = TOGGLE YES NO
NO
DQ5 =1 YES READ DQ7
DQ5 =1 YES READ DQ6
DQ7 = DATA NO FAIL
YES
DQ6 = TOGGLE YES PASS FAIL
NO
PASS
AI01369B
AI01370B
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Unlock Bypass. The Unlock Bypass instructions allow the system to program bytes to the Flash memories faster than using the standard Program instruction. The Unlock Bypass Mode is entered by first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the Unlock Bypass code, 20h (as shown in Table 79). The Flash memory then enters the Unlock Bypass Mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the Unlock Bypass Program code, A0h. The second cycle contains the program address and data. Additional data is programmed in the same manner. These instructions dispense with the initial two Unlock cycles required in the standard Program instruction, resulting in faster total Flash memory programming. During the Unlock Bypass Mode, only the Unlock Bypass Program and Unlock Bypass Reset Flash instructions are valid. To exit the Unlock Bypass Mode, the system must issue the two-cycle Unlock Bypass Reset Flash instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are Don't Care for both cycles. The Flash memory then returns to READ Mode. Erasing Flash Memory Flash Bulk Erase. The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 79. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the READ Flash memory status. During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in Programming Flash Memory, page 71. The Error Flag Bit (DQ5) returns a '1' if there has been an Erase Failure (maximum number of Erase cycles have been executed). It is not necessary to program the memory with 00h because the PSD Module automatically does this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions. Flash Sector Erase. The Sector Erase instruction uses six WRITE operations, as described in Table 79. Additional Flash Sector Erase codes and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel, without further coded cycles, if the additional bytes are transmitted in a shorter time than the time-out period of about 100s. The input of a new Sector Erase code restarts the timeout period. The status of the internal timer can be monitored through the level of the Erase Time-out Flag Bit (DQ3). If the Erase Time-out Flag Bit (DQ3) is '0,' the Sector Erase instruction has been received and the time-out period is counting. If the Erase Time-out Flag Bit (DQ3) is '1,' the time-out period has expired and the embedded algorithm is busy erasing the Flash memory sector(s). Before and during Erase time-out, any instruction other than Suspend Sector Erase and Resume Sector Erase instructions abort the cycle that is currently in progress, and reset the device to READ Mode. During a Sector Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in Programming Flash Memory, page 71. During execution of the Erase cycle, the Flash memory accepts only RESET and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed. Suspend Sector Erase. When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any address when an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 79). This allows reading of data from another Flash memory sector after the Erase cycle has been suspended. Suspend Sector Erase is accepted only during an Erase cycle and defaults to READ Mode. A Suspend Sector Erase instruction executed during an Erase timeout period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle Flag Bit (DQ6) stops toggling when the internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag Bit (DQ6) stops toggling between 0.1s and 15s after the Suspend Sector Erase instruction has been executed. The Flash memory is then automatically set to READ Mode. If an Suspend Sector Erase instruction was executed, the following rules apply: - Attempting to read from a Flash memory sector that was being erased outputs invalid data. - Reading from a Flash sector that was not being erased is valid. - The Flash memory cannot be programmed, and only responds to Resume Sector Erase and Reset Flash instructions (READ is an operation and is allowed). - If a Reset Flash instruction is received, data in the Flash memory sector that was being erased is invalid.
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Resume Sector Erase. If a Suspend Sector Erase instruction was previously executed, the erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 79.) Specific Features Flash Memory Sector Protect. Each primary and secondary Flash memory sector can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated through the JTAG Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft Express Configuration program. This automatically protects selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash memory sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The MCU can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash memory sector is ignored by the device. The Verify operation results in a READ of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can be read by the MCU through the Flash memory protection registers (in the CSIOP block). See Table 81 and Table 82.
Table 81. Sector Protection/Security Bit Definition - Flash Protection Register
Bit 7 Sec7_Prot
Note:
Bit 6 Sec6_Prot
Bit 5 Sec5_Prot
Bit 4 Sec4_Prot
Bit 3 Sec3_Prot
Bit 2 Sec2_Prot
Bit 1 Sec1_Prot
Bit 0 Sec0_Prot
Bit Definitions: Sec_Prot 1 = Primary Flash memory or secondary Flash memory Sector is write-protected. Sec_Prot 0 = Primary Flash memory or secondary Flash memory Sector is not write-protected.
Table 82. Sector Protection/Security Bit Definition - Secondary Flash Protection Register
Bit 7 Security_Bit
Note:
Bit 6 not used
Bit 5 not used
Bit 4 not used
Bit 3 Sec3_Prot
Bit 2 Sec2_Prot
Bit 1 Sec1_Prot
Bit 0 Sec0_Prot
Bit Definitions: Sec_Prot 1 = Secondary Flash memory Sector is write-protected. Sec_Prot 0 = Secondary Flash memory Sector is not write-protected. Security_Bit 0 = Security Bit in device has not been set; 1 = Security Bit in device has been set.
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Reset Flash. The Reset Flash instruction consists of one WRITE cycle (see Table 79). It can also be optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and 55h to AAAh). It must be executed after: - Reading the Flash Protection Status - An Error condition has occurred (and the device has set the Error Flag Bit (DQ5) to '1' during a Flash memory Program or Erase cycle. The Reset Flash instruction puts the Flash memory back into normal READ Mode. If an Error condition has occurred (and the device has set the Error Flag Bit (DQ5) to '1' the Flash memory is put back into normal READ Mode within 25s of the Reset Flash instruction having been issued. The Reset Flash instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ Mode within 25s. Reset (RESET) Signal. A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash memory to the READ Mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes up to 25s to return to the READ Mode. It is recommended that the Reset (RESET) pulse (except for Power-on RESET, as described on page 94) be at least 25s so that the Flash memory is always ready for the MCU to retrieve the bootstrap instructions after the reset cycle is complete. SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to Voltage Stand-by (VSTBY, PC2). If you have an external battery connected to the PSD3200, the contents of the SRAM are retained in the event of a power loss. The contents of the SRAM are retained so long as the battery voltage remains at 2V or greater. If the supply voltage falls below the battery voltage, an internal power switch-over to the battery occurs. PC4 can be configured as an output that indicates when power is being drawn from the external battery. Battery-on Indicator (VBATON, PC4) is High with the supply voltage falls below the battery voltage and the battery on Voltage Stand-by (VSTBY, PC2) is supplying power to the internal SRAM. SRAM Select (RS0), Voltage Stand-by (VSTBY, PC2) and Battery-on Indicator (VBATON, PC4) are all configured using PSDsoft Express Configuration. Sector Select and SRAM Select Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDsoft Express. The following rules apply to the equations for these signals: 1. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size. 2. Any primary Flash memory sector must not be mapped in the same memory space as another Flash memory sector. 3. A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. A secondary Flash memory sector may overlap a primary Flash memory sector. In case of overlap, priority is given to the secondary Flash memory sector. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is given to the SRAM, I/O, or Peripheral I/O.
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Example. FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any address greater than 9FFFh accesses the primary Flash memory segment 0. You can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Note: An equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 30 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest. Memory Select Configuration in Program and Data Spaces. The MCU Core has separate address spaces for Program memory and Data memory. Any of the memories within the PSD Module can reside in either space or both spaces. This is controlled through manipulation of the VM Register that resides in the CSIOP space. The VM Register is set using PSDsoft Express to have an initial value. It can subsequently be Table 83. VM Register
Bit 7 PIO_EN Bit 6 Bit 5 Bit 4 Primary FL_Data 0 = RD can't access Flash memory 1 = RD access Flash memory Bit 3 Secondary Data Bit 2 Primary FL_Code 0 = PSEN can't access Flash memory 1 = PSEN access Flash memory Bit 1 Secondary Code Bit 0 SRAM_Code 0 = PSEN can't access SRAM 1 = PSEN access SRAM
changed by the MCU so that memory mapping can be changed on-the-fly. For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the primary and secondary Flash memories. This is easily done with the VM Register by using PSDsoft Express Configuration to configure it for Boot-up and having the MCU change it when desired. Table 83 describes the VM Register. Figure 30. Priority Level of Memory and I/O Components in the PSD Module
Highest Priority
Level 1 SRAM, I /O, or Peripheral I /O Level 2 Secondary Non-Volatile Memory Level 3 Primary Flash Memory Lowest Priority
AI02867D
0 = disable PIO Mode
not used
not used
0 = RD can't access Secondary Flash memory
0 = PSEN can't access Secondary Flash memory
1= enable PIO Mode
not used
not used
1 = RD access Secondary Flash memory
1 = PSEN access Secondary Flash memory
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Separate Space Mode. Program space is separated from Data space. For example, Program Select Enable (PSEN) is used to access the program code from the primary Flash memory, while READ Strobe (RD) is used to access data from the secondary Flash memory, SRAM and I/O Port blocks. This configuration requires the VM Register to be set to 0Ch (see Figure 31). Figure 31. Separate Space Mode Combined Space Modes. The Program and Data spaces are combined into one memory space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN) or READ Strobe (RD). For example, to configure the primary Flash memory in Combined space, Bits b2 and b4 of the VM Register are set to '1' (see Figure 32).
DPLD
RS0 CSBOOT0-3 FS0-FS7
Primary Flash Memory
Secondary Flash Memory
SRAM
CS OE
CS OE
CS OE
PSEN RD
AI02869C
Figure 32. Combined Space Mode
DPLD
RS0 CSBOOT0-3 FS0-FS7
Primary Flash Memory
Secondary Flash Memory
SRAM
RD
CS OE
CS OE
CS OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
VM REG BIT 2
RD
VM REG BIT 0
AI02870C
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Page Register The 8-bit Page Register increases the addressing capability of the MCU Core by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the CPLD for general logic. Figure 33 shows the Page Register. The eight flipflops in the register are connected to the internal data bus D0-D7. The MCU can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h.
Figure 33. Page Register
RESET
D0 D1 D0 - D7 D2 D3 D4 D5 D6 R/ W D7
Q0 Q1 Q2 Q3 Q4 Q5
PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 DPLD AND CPLD
INTERNAL PSD MODULE SELECTS AND LOGIC
Q6 PGR7 Q7
PAGE REGISTER
PLD
AI05799
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PLDS The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs in PSDsoft Express, the logic is programmed into the device and available upon Power-up. The PSD Module contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The DPLD performs address decoding for Select signals for PSD Module components, such as memory, registers, and I/O ports. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. The Turbo Bit in PSD Module The PLDs can minimize power consumption by switching off when inputs remain unchanged for an extended time of about 70ns. Resetting the Turbo Bit to '0' (Bit 3 of PMMR0) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo Mode off increases propagation delays while reducing power consumption. See POWER MANAGEMENT, page 90 for details on setting the Turbo Bit.
Table 84. DPLD and CPLD Inputs
Input Source MCU Address Bus MCU Control Signals RESET Power-down Port A Input Macrocells(1) Port B Input Macrocells Port C Input Macrocells Port D Inputs Page Register Macrocell AB Feedback Macrocell BC Feedback Flash memory Program Status Bit Input Name A15-A0 PSEN, RD, WR, ALE RST PDN PA7-PA0 PB7-PB0 PC2-4, PC7 PD2-PD1 PGR7-PGR0 MCELLAB.FB7FB0 MCELLBC.FB7FB0 Ready/Busy No. of Signals 16 4 1 1 8 8 4 2 8 8 8 1
Note: 1. These inputs are not available in the 52-pin package.
Figure 34. PLD Diagram
8 DATA BUS 73 PAGE REGISTER DECODE PLD 8 4 1 1 2 PLD INPUT BUS 16 OUTPUT MACROCELL FEEDBACK PRIMARY FLASH MEMORY SELECTS SECONDARY NON-VOLATILE MEMORY SELECTS SRAM SELECT CSIOP SELECT PERIPHERAL SELECTS DIRECT MACROCELL ACCESS FROM MCU DATA BUS
CPLD PT ALLOC.
16 OUTPUT MACROCELL
73
MACROCELL ALLOC. I/O PORTS
MCELLAB TO PORT A OR B(1) MCELLBC TO PORT B OR C
8
8 2
20 INPUT MACROCELL (PORT A,B,C)
EXTERNAL CHIP SELECTS TO PORT D
DIRECT MACROCELL INPUT TO MCU DATA BUS 20 2 INPUT MACROCELL & INPUT PORTS PORT D INPUTS
AI06600
Note: 1. Ports A is not available in the 52-pin package
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Decode PLD (DPLD) The DPLD, shown in Figure 35, is used for decoding the address for PSD Module and external components. The DPLD can be used to generate the following decode signals: s Up to 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each).
s
Up to 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) 1 internal SRAM Select (RS0) signal (two product terms) 1 internal CSIOP Select signal (selects the PSD Module registers) 2 internal Peripheral Select signals (Peripheral I/O Mode).
s
s
s
Figure 35. DPLD Logic Array
3 3 3 3 (INPUTS) I /O PORTS (PORT A,B,C)1 MCELLAB.FB [7:0] (FEEDBACKS) MCELLBC.FB [7:0] (FEEDBACKS) PGR0 -PGR7 A[15:0]2 PD[2:1] PDN (APD OUTPUT) PSEN, RD, WR, ALE2 RESET 2 (20) 3 (8) 3 (8) 3 (8) 3 (16) 3 (2) 3 (1) 3 (4) (1) 2 RD_BSY (1) 1 1 1 CSIOP PSEL0 PSEL1 PERIPHERAL I/O MODE SELECT
AI06601
CSBOOT 0 CSBOOT 1 CSBOOT 2 CSBOOT 3
3
FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 8 PRIMARY FLASH MEMORY SECTOR SELECTS
RS0
SRAM SELECT I/O DECODER SELECT
Note: 1. Port A inputs are not available in the 52-pin package 2. Inputs from the MCU module
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Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate External Chip Select (ECS1-ECS2), routed to Port D. As shown in Figure 34, the CPLD has the following blocks: s 20 Input Macrocells (IMC)
s s s s
16 Output Macrocells (OMC) Macrocell Allocator Product Term Allocator AND Array capable of generating up to 137 product terms Four I/O Ports.
Each of the blocks are described in the sections that follow. The Input Macrocells (IMC) and Output Macrocells (OMC) are connected to the PSD Module internal data bus and can be directly accessed by the MCU. This enables the MCU software to load data into the Output Macrocells (OMC) or read data from both the Input and Output Macrocells (IMC and OMC). This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND Array as required in most standard PLD macrocell architectures.
s
Figure 36. Macrocell and I/O Port
PLD INPUT BUS PRODUCT TERMS FROM OTHER MACROCELLS MCU ADDRESS / DATA BUS TO OTHER I/O PORTS
CPLD MACROCELLS
PT PRESET PRODUCT TERM ALLOCATOR MCU DATA IN MCU LOAD DATA LOAD CONTROL
I/O PORTS
LATCHED ADDRESS OUT DATA WR
I/O PIN
D Q MUX
AND ARRAY
UP TO 10 PRODUCT TERMS MACROCELL OUT TO MCU CPLD OUTPUT
PR DI LD PT CLOCK D/T MUX Q COMB. /REG SELECT CPLD OUTPUT MACROCELL TO I/O PORT ALLOC. WR PT CLEAR PDR INPUT SELECT
PLD INPUT BUS
GLOBAL CLOCK CLOCK SELECT
D/T/JK FF SELECT CK CL
MUX
POLARITY SELECT
D
Q DIR REG.
PT OUTPUT ENABLE (OE) MACROCELL FEEDBACK I/O PORT INPUT
INPUT MACROCELLS
MUX QD
PT INPUT LATCH GATE/CLOCK MUX ALE
QD G
AI06602
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Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are connected to Ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and are named as McellBC0-McellBC7. If an McellAB output is not assigned to a specific pin in PSDsoft, the Macrocell Allocator block assigns it to either Port A or B. The same is true for a McellBC output on Port B or C. Table 85 shows the macrocells and port assignment.
The Output Macrocell (OMC) architecture is shown in Figure 37. The flip-flop in the Output Macrocell (OMC) block can be configured as a D, T, JK, or SR type in PSDsoft. The flip-flop's clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms.
Table 85. Output Macrocell Port and Data Bit Assignments
Output Macrocell McellAB0 McellAB1 McellAB2 McellAB3 McellAB4 McellAB5 McellAB6 McellAB7 McellBC0 McellBC1 McellBC2 McellBC3 McellBC4 McellBC5 McellBC6 McellBC7 Port Assignment(1,2) Port A0, B0 Port A1, B1 Port A2, B2 Port A3, B3 Port A4, B4 Port A5, B5 Port A6, B6 Port A7, B7 Port B0 Port B1 Port B2, C2 Port B3, C3 Port B4, C4 Port B5 Port B6 Port B7, C7 Native Product Terms 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 Maximum Borrowed Product Terms 6 6 6 6 6 6 6 6 5 5 5 5 6 6 6 6 Data Bit for Loading or Reading D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Note: 1. McellAB0-McellAB7 can only be assigned to Port B in the 52-pin package. 2. Port PC0, PC1, PC5, and PC6 are assigned to JTAG pins and are not available as Macrocell outputs.
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Product Term Allocator The CPLD has a Product Term Allocator. PSDsoft uses the Product Term Allocator to borrow and place product terms from one macrocell to another. The following list summarizes how product terms are allocated: s McellAB0-McellAB7 all have three native product terms and may borrow up to six more
s
McellBC0-McellBC3 all have four native product terms and may borrow up to five more McellBC4-McellBC7 all have four native product terms and may borrow up to six more.
s
Each macrocell may only borrow product terms from certain other macrocells. Loading and Reading the Output Macrocells (OMC). The Output Macrocells (OMC) block occupies a memory location in the MCU address Figure 37. CPLD Output Macrocell
MASK REG.
space, as defined by the CSIOP block (see "I/O PORTS (PSD MODULE), page 84). The flip-flops in each of the 16 Output Macrocells (OMC) can be loaded from the data bus by a MCU. Loading the Output Macrocells (OMC) with data from the MCU takes priority over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. Data can be loaded to the Output Macrocells (OMC) on the trailing edge of WRITE Strobe (WR, edge loading) or during the time that WRITE Strobe (WR) is active (level loading). The method of loading is specified in PSDsoft Express Configuration.
MACROCELL CS RD
MCU DATA BUS
D [ 7:0]
PT ALLOCATOR
WR DIRECTION REGISTER ENABLE (.OE) PRESET(.PR) COMB/REG SELECT
AND ARRAY
PT PT DIN PR
PLD INPUT BUS
MUX PT LD POLARITY SELECT CLEAR (.RE) PT CLK CLKIN MUX IN CLR PROGRAMMABLE FF (D / T/JK /SR) PORT DRIVER Q MACROCELL ALLOCATOR
I/O PIN
FEEDBACK (.FB) PORT INPUT INPUT MACROCELL
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The OMC Mask Register. There is one Mask Register for each of the two groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Output Macrocells (OMC). The default value for the Mask Registers is 00h, which allows loading of the Output Macrocells (OMC). When a given bit in a Mask Register is set to a '1,' the MCU is blocked from writing to the associated Output Macrocells (OMC). For example, suppose McellAB0McellAB3 are being used for a state machine. You would not want a MCU write to McellAB to overwrite the state machine registers. Therefore, you would want to load the Mask Register for McellAB (Mask Macrocell AB) with the value 0Fh. The Output Enable of the OMC. The Output Macrocells (OMC) block can be connected to an I/ O port pin as a PLD output. The output enable of each port pin driver is controlled by a single product term from the AND Array, ORed with the Direction Register output. The pin is enabled upon Power-up if no output enable equation is defined and if the pin is declared as a PLD output in PSDsoft Express. Figure 38. Input Macrocell
MCU DATA BUS D [ 7:0]
If the Output Macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array. Input Macrocells (IMC) The CPLD has 20 Input Macrocells (IMC), one for each pin on Ports A and B, and 4 on Port C. The architecture of the Input Macrocells (IMC) is shown in Figure 38. The Input Macrocells (IMC) are individually configurable, and can be used as a latch, register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The outputs of the Input Macrocells (IMC) can be read by the MCU through the internal data bus. The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND Array or the MCU Address Strobe (ALE). Each product term output is used to latch or clock four Input Macrocells (IMC). Port inputs 3-0 can be controlled by one product term and 7-4 by another.
INPUT MACROCELL _ RD ENABLE ( .OE ) OUTPUT MACROCELLS BC AND MACROCELL AB
DIRECTION REGISTER
PT AND ARRAY
PLD INPUT BUS
I/O PIN PT
PORT DRIVER
MUX
Q
D MUX
PT ALE
D FF FEEDBACK Q D G LATCH INPUT MACROCELL
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I/O PORTS (PSD MODULE) There are four programmable I/O ports: Ports A, B, C, and D in the PSD Module. Each of the ports is eight bits except Port D. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Express Configuration or by the MCU writing to on-chip registers in the CSIOP space. Port A is not available in the 52-pin package. General Port Architecture The general architecture of the I/O Port block is shown in Figure 39. In general, once the purpose for a port pin has been defined, that pin is no longer available for other purposes. Exceptions are noted. As shown in Figure 39, the ports contain an output multiplexer whose select signals are driven by the configuration bits in the Control Registers (Ports A Figure 39. General I/O Port Architecture
DATA OUT REG. D WR ADDRESS ALE D G Q ADDRESS OUTPUT MUX PORT PIN Q DATA OUT
and B only) and PSDsoft Express Configuration. Inputs to the multiplexer include the following: s Output data from the Data Out register
s s s
Latched address outputs CPLD macrocell output External Chip Select (ECS1-ECS2) from the CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and can be read by the MCU. The Data Out and macrocell outputs, Direction and Control Registers, and port pin input are all connected to the Port Data Buffer (PDB).
MACROCELL OUTPUTS EXT CS READ MUX P D B
(1)
MCU DATA BUS
OUTPUT SELECT DATA IN
CONTROL REG. D WR DIR REG. D WR Q Q
ENABLE OUT
ENABLE PRODUCT TERM (.OE) INPUT MACROCELL CPLD-INPUT
AI07873
Note: 1. Control Register is not available in Ports C and D.
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The Port pin's tri-state output driver enable is controlled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in the PSDsoft, then the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB) feedback path allows the MCU to check the contents of the registers. Ports A, B, and C have embedded Input Macrocells (IMC). The Input Macrocells (IMC) can be configured as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by Address Strobe (ALE) or a product term from the PLD AND Array. The outputs from the Input Macrocells (IMC) drive the PLD input bus and can be read by the MCU. See Input Macrocell, page 83. Port Operating Modes The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft, some by the MCU writing to the Control Registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft must be programmed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data Port, Address Input, and Peripheral I/O Modes are the only modes that must be defined before programming the device. All other modes can be changed by the MCU at run-time. See Application Note AN1171 for more detail. Table 86 summarizes which modes are available on each port. Table 89 shows how and where the different modes are configured. Each of the port operating modes are described in the following sections. MCU I/O Mode In the MCU I/O Mode, the MCU uses the I/O Ports block to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD Module are mapped into the MCU address space. The addresses of the ports are listed in Table 77, page 67. A port pin can be put into MCU I/O Mode by writing a '0' to the corresponding bit in the Control Register. The MCU I/O direction may be changed by writing to the corresponding bit in the Direction Register, or by the output enable product term (see Peripheral I/O Mode, page 85). When the pin is configured as an output, the content of the Data Out Register drives the pin. When configured as an input, the MCU can read the port input through the Data In buffer. See Figure 39, page 84. Ports C and D do not have Control Registers, and are in MCU I/O Mode by default. They can be used for PLD I/O if equations are written for them in PSDabel. PLD I/O Mode The PLD I/O Mode uses a port as an input to the CPLD's Input Macrocells (IMC), and/or as an output from the CPLD's Output Macrocells (OMC). The output can be tri-stated with a control signal. This output enable control signal can be defined by a product term from the PLD, or by resetting the corresponding bit in the Direction Register to '0.' The corresponding bit in the Direction Register must not be set to '1' if the pin is defined for a PLD input signal in PSDsoft. The PLD I/O Mode is specified in PSDsoft by declaring the port pins, and then writing an equation assigning the PLD I/ O to a port. Address Out Mode Address Out Mode can be used to drive latched MCU addresses on to the port pins. These port pins can, in turn, drive external devices. Either the output enable or the corresponding bits of both the Direction Register and Control Register must be set to a '1' for pins to use Address Out Mode. This must be done by the MCU at run-time. See Table 88 for the address output pin assignments on Ports A and B for various MCUs. Peripheral I/O Mode Peripheral I/O Mode can be used to interface with external peripherals. In this mode, all of Port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O Mode is enabled by setting Bit 7 of the VM Register to a '1.' Figure 40 shows how Port A acts as a bi-directional buffer for the MCU data bus if Peripheral I/O Mode is enabled. An equation for PSEL0 and/or PSEL1 must be written in PSDsoft. The buffer is tri-stated when PSEL0 or PSEL1 is low (not active). The PSEN signal should be "ANDed" in the PSEL equations to disable the buffer when PSEL resides in the data space. JTAG In-System Programming (ISP) Port C is JTAG compliant, and can be used for InSystem Programming (ISP). For more information on the JTAG Port, see PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE, page 95.
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Figure 40. Peripheral I/O Mode
RD PSEL0 PSEL PSEL1 D0 - D7 DATA BUS
VM REGISTER BIT 7
PA0 - PA7
WR
AI02886
Table 86. Port Operating Modes
Port Mode MCU I/O PLD I/O McellAB Outputs McellBC Outputs Additional Ext. CS Outputs PLD Inputs Address Out Peripheral I/O JTAG ISP Yes Yes No No Yes Yes (A7 - 0) Yes No Port A(1) Yes Yes Yes No Yes Yes (A7 - 0) No No Port B Yes No Yes(2) No Yes No No Yes(3) Port C Yes No No Yes Yes No No No Port D
Note: 1. Port A is not available in the 52-pin package. 2. On pins PC2, PC3, PC4, and PC7 only. 3. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.
Table 87. Port Operating Mode Settings
Mode MCU I/O PLD I/O Address Out (Port A,B) Peripheral I/O (Port A) Defined in PSDsoft Declare pins only Logic equations Declare pins only Logic equations (PSEL0 & 1) 0 N/A 1 N/A Control Register Setting(1) Direction Register Setting(1) 1 = output, 0 = input (Note 2) (Note 2) 1 (Note 2) N/A VM Register Setting(1) N/A N/A N/A PIO Bit = 1
Note: 1. N/A = Not Applicable 2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product term (.oe) from the CPLD AND Array.
Table 88. I/O Port Latched Address Output Assignments
Port A (PA3-PA0) Address a3-a0 Port A (PA7-PA4) Address a7-a4 Port B (PB3-PB0) Address a3-a0 Port B (PB7-PB4) Address a7-a4
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Port Configuration Registers (PCR) Each Port has a set of Port Configuration Registers (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in Table 77, page 67. The addresses in Table 79, page 69 are the offsets in hexadecimal from the base of the CSIOP register. The pins of a port are individually configurable and each bit in the register controls its respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three Port Configuration Registers (PCR), shown in Table 89, are used for setting the Port configurations. The default Power-up state for each register in Table 89 is 00h. Control Register. Any bit reset to '0' in the Control Register sets the corresponding port pin to MCU I/O Mode, and a '1' sets it to Address Out Mode. The default mode is MCU I/O. Only Ports A and B have an associated Control Register. Direction Register. The Direction Register, in conjunction with the output enable (except for Port D), controls the direction of data flow in the I/O Ports. Any bit set to '1' in the Direction Register causes the corresponding pin to be an output, and any bit set to '0' causes it to be an input. The default mode for all port pins is input. Figure 39, page 84 shows the Port Architecture diagrams for Ports A/B and C, respectively. The direction of data flow for Ports A, B, and C are controlled not only by the direction register, but also by the output enable product term from the PLD AND Array. If the output enable product term is not active, the Direction Register has sole control of a given pin's direction. An example of a configuration for a Port with the three least significant bits set to output and the remainder set to input is shown in Table 92. Since Port D only contains two pins, the Direction Register for Port D has only two bits active. Drive Select Register. The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should be used for pins configured as Open Drain. A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to a '1.' The default pin drive is CMOS.
Note: The slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive Register is set to '1.' The default rate is slow slew. Table 93, page 88 shows the Drive Register for Ports A, B, C, and D. It summarizes which pins can be configured as Open Drain outputs and which pins the slew rate can be set for. Table 89. Port Configuration Registers (PCR)
Register Name Control Direction Drive Select(1) A,B A,B,C,D A,B,C,D Port MCU Access WRITE/READ WRITE/READ WRITE/READ
Note: 1. See Table 93 for Drive Register Bit definition.
Table 90. Port Pin Direction Control, Output Enable P.T. Not Defined
Direction Register Bit 0 1 Input Output Port Pin Mode
Table 91. Port Pin Direction Control, Output Enable P.T. Defined
Direction Register Bit 0 0 1 1 Output Enable P.T. 0 1 0 1 Port Pin Mode Input Output Output Output
Table 92. Port Direction Assignment Example
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 1 Bit 1 1 Bit 0 1
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Port Data Registers The Port Data Registers, shown in Table 94, are used by the MCU to write data to or read data from the ports. Table 94 shows the register name, the ports having each register type, and MCU access for each register type. The registers are described below. Data In. Port pins are connected directly to the Data In buffer. In MCU I/O Input Mode, the pin input is read through the Data In buffer. Data Out Register. Stores output data written by the MCU in the MCU I/O Output Mode. The contents of the Register are driven out to the pins if the Direction Register or the output enable product term is set to '1.' The contents of the register can also be read back by the MCU. Output Macrocells (OMC). The CPLD Output Macrocells (OMC) occupy a location in the MCU's address space. The MCU can read the output of the Output Macrocells (OMC). If the OMC Mask Table 93. Drive Register Pin Assignment
Drive Register Port A Port B Port C Port D Bit 7 Open Drain Open Drain Open Drain NA(1) Bit 6 Open Drain Open Drain Open Drain NA(1) Bit 5 Open Drain Open Drain Open Drain NA(1) Bit 4 Open Drain Open Drain Open Drain NA(1) Bit 3 Slew Rate Slew Rate Open Drain NA(1) Bit 2 Slew Rate Slew Rate Open Drain Slew Rate Bit 1 Slew Rate Slew Rate Open Drain Slew Rate Bit 0 Slew Rate Slew Rate Open Drain NA(1)
Register Bits are not set, writing to the macrocell loads data to the macrocell flip-flops. See PLDs, page 78. OMC Mask Register. Each OMC Mask Register Bit corresponds to an Output Macrocell (OMC) flipflop. When the OMC Mask Register Bit is set to a '1,' loading data into the Output Macrocell (OMC) flip-flop is blocked. The default value is '0' or unblocked. Input Macrocells (IMC). The Input Macrocells (IMC) can be used to latch or store external inputs. The outputs of the Input Macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU. See PLDs, page 78. Enable Out. The Enable Out register can be read by the MCU. It contains the output enable values for a given port. A '1' indicates the driver is in output mode. A '0' indicates the driver is in tri-state and the pin is in input mode.
Note: 1. NA = Not Applicable.
Table 94. Port Data Registers
Register Name Data In Data Out Output Macrocell Mask Macrocell Input Macrocell Enable Out Port A,B,C,D A,B,C,D A,B,C A,B,C A,B,C A,B,C READ - input on pin WRITE/READ READ - outputs of macrocells WRITE - loading macrocells flip-flop WRITE/READ - prevents loading into a given macrocell READ - outputs of the Input Macrocells READ - the output enable control of the port driver MCU Access
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Ports A and B - Functionality and Structure Ports A and B have similar functionality and structure, as shown in Figure 39, page 84. The two ports can be configured to perform one or more of the following functions: s MCU I/O Mode
s
s
Open Drain - Port C pins can be configured in Open Drain Mode Battery Backup features - PC2 can be configured for a battery input supply, Voltage Stand-by (VSTBY).
s
CPLD Output - Macrocells McellAB7-McellAB0 can be connected to Port A or Port B. McellBC7McellBC0 can be connected to Port B or Port C. CPLD Input - Via the Input Macrocells (IMC). Latched Address output - Provide latched address output as per Table 88. Open Drain/Slew Rate - pins PA3-PA0 and PB3-PB0 can be configured to fast slew rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain Mode. Peripheral Mode - Port A only (80-pin package)
s s
s
s
Port C - Functionality and Structure Port C can be configured to perform one or more of the following functions (see Figure 39, page 84): s MCU I/O Mode
s
PC4 can be configured as a Battery-on Indicator (VBATON), indicating when VCC is less than VBAT. Port D - Functionality and Structure Port D has two I/O pins (only one pin, PD1, in the 52-pin package). This port does not support Address Out Mode, and therefore no Control Register is required. Of the eight bits in the Port D registers, only Bits 2 and 1 are used to configure pins PD2 and PD1. Port D can be configured to perform one or more of the following functions: s MCU I/O Mode;
s
CPLD Output - External Chip Select (ECS1ECS2), each ECS consists of one product term that can be configured active high or low; CPLD Input - direct input to the CPLD, no Input Macrocells (IMC); and Slew rate - pins can be set up for fast slew rate
CPLD Output - McellBC[2, 3. 4, 7] outputs can be connected to Port C. CPLD Input - via the Input Macrocells (IMC) on pins PC2, PC3, PC4, and PC7. In-System Programming (ISP) - Port pins PC0, PC1, PC5, and PC6 are dedicated for JTAG ISP programming (TMS, TCK, TDI, TDO, see PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE, page 95, for more information on JTAG programming.)
s
s
s
s
Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions: s CLKIN (PD1) as input to the macrocells flipflops and APD counter, and
s
PSD Chip Select Input (CSI, PD2). Driving this signal High disables the Flash memory, SRAM and CSIOP.
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POWER MANAGEMENT All PSD Module offers configurable power saving options. These options may be used individually or in combinations, as follows: s The primary and secondary Flash memory, and SRAM blocks are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into Standby Mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory "wakes up," changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve Memory Standby Mode when no inputs are changing--it happens automatically. The PLD sections can also achieve Standby Mode when its inputs are not changing, as described in the sections on the Power Management Mode Registers (PMMR). s As with the Power Management Mode, the Automatic Power Down (APD) block allows the PSD Module to reduce to stand-by current automatically. The APD Unit can also block MCU address/data signals from reaching the memories and PLDs. Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD Unit initiates Power-down Mode (if enabled). Figure 41. APD Unit
APD EN PMMR0 BIT 1=1 TRANSITION DETECTION ALE CLR PD CSIOP SELECT FLASH SELECT EDGE DETECT PD PLD SRAM SELECT POWER DOWN (PDN) SELECT DISABLE BUS INTERFACE
s
s
Once in Power-down Mode, all address/data signals are blocked from reaching memory and PLDs, and the memories are deselected internally. This allows the memory and PLDs to remain in Standby Mode even if the address/ data signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of Stand-by Mode, but not the memories. PSD Chip Select Input (CSI, PD2) can be used to disable the internal memories, placing them in Standby Mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD Unit. There is a slight penalty in memory access time when PSD Chip Select Input (CSI, PD2) makes its initial transition from deselected to selected. The PMMRs can be written by the MCU at runtime to manage power. The PSD Module supports "blocking bits" in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure 44 and Figure 45). Significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations.
RESET CSI CLKIN
APD COUNTER
DISABLE FLASH/SRAM
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The PSD Module has a Turbo Bit in PMMR0.This bit can be set to turn the Turbo Mode off (the default is with Turbo Mode turned on). While Turbo Mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo Mode is on. When the Turbo Mode is on, there is a significant DC current component and the AC component is higher. Automatic Power-down (APD) Unit and Powerdown Mode. The APD Unit, shown in Figure 41, puts the PSD Module into Power-down Mode by monitoring the activity of Address Strobe (ALE). If the APD Unit is enabled, as soon as activity on Address Strobe (ALE) stops, a four-bit counter starts counting. If Address Strobe (ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down (PDN) goes High, and the PSD Module enters Power-down Mode, as discussed next. Power-down Mode. By default, if you enable the APD Unit, Power-down Mode is automatically enabled. The device enters Power-down Mode if Address Strobe (ALE) remains inactive for fifteen periods of CLKIN (PD1). The following should be kept in mind when the PSD Module is in Power-down Mode: s If Address Strobe (ALE) starts pulsing again, the PSD Module returns to normal Operating mode. The PSD Module also returns to normal Operating mode if either PSD Chip Select Input (CSI, PD2) is Low or the RESET input is High. s The MCU address/data bus is blocked from all memory and PLDs. s Various signals can be blocked (prior to Powerdown Mode) from entering the PLDs by setting the appropriate bits in the PMMR registers. The blocked signals include MCU control signals and the common CLKIN (PD1). Note: Blocking CLKIN (PD1) from the PLDs does not block CLKIN (PD1) from the APD Unit. s All memories enter Standby Mode and are drawing standby current. However, the PLD and I/O ports blocks do not go into Standby Mode because you don't want to have to wait for the logic and I/O to "wake-up" before their outputs can change. See Table 95 for Power-down Mode effects on PSD Module ports.
s
Typical standby current is of the order of microamperes. These standby current values assume that there are no transitions on any PLD input. Other Power Saving Options. The PSD Module offers other reduced power saving options that are independent of the Power-down Mode. Except for the SRAM Stand-by and PSD Chip Select Input (CSI, PD2) features, they are enabled by setting bits in PMMR0 and PMMR2.
Figure 42. Enable Power-down Flow Chart
RESET
Enable APD Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD by setting PMMR0 bits 4 and 5 and PMMR2 bits 2 through 6.
No
ALE idle for 15 CLKIN clocks? Yes PSD Module in Power Down Mode
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Table 95. Power-down Mode's Effect on Ports
Port Function MCU I/O PLD Out Address Out Peripheral I/O Pin Level No Change No Change Undefined Tri-State
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PLD Power Management The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By setting the bit to '1,' the Turbo Mode is off and the PLDs consume the specified stand-by current when the inputs are not switching for an extended time of 70ns. The propagation delay time is increased by 10ns (for a 5V device) after the Turbo Bit is set to '1' (turned off) when the inputs change at a composite frequency of less than 15MHz. When the Turbo Bit is reset to '0' (turned on), the PLDs run at full power and speed. The Turbo Bit affects the PLD's DC power, AC power, and propagation delay. When the Turbo Mode is off, the PSD3200 input clock frequency is reduced by 5MHz from the maximum rated clock frequency. Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power consumption. SRAM Standby Mode (Battery Backup). The SRAM in the PSD Module supports a battery backup mode in which the contents are retained in the event of a power loss. The SRAM has Voltage Stand-by (VSTBY, PC2) that can be connected to an external battery. When VCC becomes lower than VSTBY then the SRAM automatically connects to Voltage Stand-by (VSTBY, PC2) as a power source. The SRAM Standby Current (ISTBY) is typically 0.5 A. The SRAM data retention voltage is 2V minimum. The Battery-on Indicator (VBATON) can be routed to PC4. This signal indicates when the VCC has dropped below VSTBY. PSD Chip Select Input (CSI, PD2) PD2 of Port D can be configured in PSDsoft Express as PSD Chip Select Input (CSI). When Low, the signal selects and enables the PSD Module Flash memory, SRAM, and I/O blocks for READ or WRITE operations. A High on PSD Chip Select Input (CSI, PD2) disables the Flash memory, and SRAM, and reduces power consumption. However, the PLD and I/O signals remain operational when PSD Chip Select Input (CSI, PD2) is High. Input Clock CLKIN (PD1) can be turned off, to the PLD to save AC power consumption. CLKIN (PD1) is an input to the PLD AND Array and the Output Macrocells (OMC). During Power-down Mode, or, if CLKIN (PD1) is not being used as part of the PLD logic equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from the PLD AND Array or the Macrocells block by setting Bits 4 or 5 to a '1' in PMMR0. Input Control Signals The PSD Module provides the option to turn off the MCU signals (WR, RD, PSEN, and Address Strobe (ALE)) to the PLD to save AC power consumption. These control signals are inputs to the PLD AND Array. During Power-down Mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They are disconnected from the PLD AND Array by setting Bits 2, 3, 4, 5, and 6 to a '1' in PMMR2.
Table 96. Power Management Mode Registers PMMR0
Bit 0 Bit 1 Bit 2 X APD Enable 1 = on Automatic Power-down (APD) is enabled. X 0 Not used, and should be set to zero. 0 Not used, and should be set to zero. 0 = off Automatic Power-down (APD) is disabled.
0 = on PLD Turbo Mode is on Bit 3 PLD Turbo 1 = off 0 = on Bit 4 PLD Array clk PLD Turbo Mode is off, saving power. PSD3200 operates at 5MHz below the maximum rated clock frequency CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN (PD1) Powers-up the PLD when Turbo Bit is '0.'
1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power. 0 = on CLKIN (PD1) input to the PLD macrocells is connected. Bit 5 Bit 6 Bit 7 PLD MCell clk 1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power. X X 0 0 Not used, and should be set to zero. Not used, and should be set to zero.
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Table 97. Power Management Mode Registers PMMR2
Bit 0 Bit 1 Bit 2 X X PLD Array WR PLD Array RD PLD Array PSEN PLD Array ALE X X 0 0 Not used, and should be set to zero. Not used, and should be set to zero.
0 = on WR input to the PLD AND Array is connected. 1 = off WR input to PLD AND Array is disconnected, saving power. 0 = on RD input to the PLD AND Array is connected. 1 = off RD input to PLD AND Array is disconnected, saving power. 0 = on PSEN input to the PLD AND Array is connected. 1 = off PSEN input to PLD AND Array is disconnected, saving power. 0 = on ALE input to the PLD AND Array is connected. 1 = off ALE input to PLD AND Array is disconnected, saving power. 0 0 Not used, and should be set to zero. Not used, and should be set to zero.
Bit 3
Bit 4
Bit 5 Bit 6 Bit 7
Note: The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers.
Table 98. APD Counter Operation
APD Enable Bit 0 1 1 ALE Level X Pulsing 0 or 1 Not Counting Not Counting Counting (Generates PDN after 15 Clocks) APD Counter
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RESET TIMING AND DEVICE STATUS AT RESET Upon Power-up, the PSD Module requires a Reset (RESET) pulse of duration tNLNH-PO after VCC is steady. During this period, the device loads internal configurations, clears some of the registers and sets the Flash memory into operating mode. The Flash memory is reset to the READ Mode upon Power-up. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must all be Low. Any Flash memory WRITE cycle initiation is prevented automatically when VDD is below VLKO. Warm RESET Once the device is up and running, the PSD Module can be reset with a pulse of a much shorter duration, tNLNH.
I/O Pin, Register and PLD Status at RESET Table 99 shows the I/O pin, register and PLD status during Power-on RESET, Warm RESET, and Power-down Mode. PLD outputs are always valid during Warm RESET, and they are valid in Poweron RESET once the internal Configuration bits are loaded. This loading is completed typically long before the VCC ramps up to operating level. Once the PLD is active, the state of the outputs are determined by the PLD equations. Reset of Flash Memory Erase and Program Cycles A Reset (RESET) also resets the internal Flash memory state machine. During a Flash memory Program or Erase cycle, Reset (RESET) terminates the cycle and returns the Flash memory to the READ Mode within a period of tNLNH-A.
Figure 43. Reset (RESET) Timing
VCC
VCC(min) tNLNH tNLNH-A Warm Reset
tNLNH-PO Power-On Reset
RESET
AI07874
Table 99. Status During Power-on RESET, Warm RESET and Power-down Mode
Port Configuration MCU I/O PLD Output Address Out Peripheral I/O Power-On RESET Input mode Valid after internal PSD configuration bits are loaded Tri-stated Tri-stated Warm RESET Input mode Valid Tri-stated Tri-stated Power-down Mode Unchanged Depends on inputs to PLD (addresses are blocked in PD Mode) Not defined Tri-stated
Register PMMR0 and PMMR2 Macrocells flip-flop status
Power-On RESET Cleared to '0' Cleared to '0' by internal Power-on RESET Initialized, based on the selection in PSDsoft Configuration menu Cleared to '0'
Warm RESET Unchanged Depends on .re and .pr equations Initialized, based on the selection in PSDsoft Configuration menu Cleared to '0'
Power-down Mode Unchanged Depends on .re and .pr equations Unchanged Unchanged
VM Register(1) All other registers
Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to '0' on Power-on RESET or Warm RESET.
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PSD33XX
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE TDI, and TDO). They are used to speed Program The JTAG Serial Interface pins (TMS, TCK, TDI, and Erase cycles by indicating status on PDS TDO) are dedicated pins on Port C (see Table signals instead of having to scan the status out se100). All memory blocks (primary and secondary rially using the standard JTAG channel. See AppliFlash memory), PLD logic, and PSD Module Concation Note AN1153. figuration Register Bits may be programmed through the JTAG Serial Interface block. A blank TERR indicates if an error has occurred when device can be mounted on a printed circuit board erasing a sector or programming a byte in Flash and programmed using JTAG. memory. This signal goes Low (active) when an Error condition occurs, and stays Low until an The standard JTAG signals (IEEE 1149.1) are "ISC_CLEAR" command is executed or a chip ReTMS, TCK, TDI, and TDO. Two additional signals, set (RESET) pulse is received after an TSTAT and TERR, are optional JTAG extensions used to speed up Program and Erase cycles. "ISC_DISABLE" command. TSTAT behaves the same as Ready/Busy. TSTAT By default, on a blank device (as shipped from the factory or after erasure), four pins on Port C are is High when the PSD Module device is in READ the basic JTAG signals TMS, TCK, TDI, and TDO. Mode (primary and secondary Flash memory contents can be read). TSTAT is Low when Flash Standard JTAG Signals memory Program or Erase cycles are in progress, At power-up, the standard JTAG pins are inputs, and also when data is being written to the secondwaiting for a JTAG serial command from an exterary Flash memory. nal JTAG controller device (such as FlashLINK or TSTAT and TERR can be configured as openAutomated Test Equipment). When the enabling drain type signals during an "ISC_ENABLE" comcommand is received, TDO becomes an output mand. and the JTAG channel is fully functional. The Security and Flash Memory Protection same command that enables the JTAG channel may optionally enable the two additional JTAG sigWhen the Security Bit is set, the device cannot be nals, TSTAT and TERR. read on a Device Programmer or through the JTAG Port. When using the JTAG Port, only a Full The RESET input to the PS3200 should be active Chip Erase command is allowed. during JTAG programming. The active RESET puts the MCU module into RESET Mode while the All other Program, Erase, and Verify commands PSD Module is being programmed. See Applicaare blocked. Full Chip Erase returns the part to a tion Note AN1153 for more details on JTAG Innon-secured, blank state. The Security Bit can be System Programming (ISP). set in PSDsoft Express Configuration. The PSD33XX Devices supports JTAG In-SysAll primary and secondary Flash memory sectors tem-Configuration (ISC) commands, but not can individually be sector protected against eraBoundary Scan. The PSDsoft Express software sures. The sector protect bits can be set in PSDtool and FlashLINK JTAG programming cable imsoft Express Configuration. plement the JTAG In-System-Configuration (ISC) commands. INITIAL DELIVERY STATE When delivered from ST, the PSD33XX Devices Table 100. JTAG Port Signals have all bits in the memory and PLDs set to '1.' Port C Pin JTAG Signals Description The code, configuration, and PLD logic are loaded using the programming procedure. Information for PC0 TMS Mode Select programming the device is available directly from ST. Please contact your local sales representaPC1 TCK Clock tive.
PC3 TSTAT TERR TDI TDO Status (optional) PC4 PC5 PC6 Error flag (optional) Serial Data In Serial Data Out
JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by an "ISC_ENABLE" command received over the four standard JTAG signals (TMS, TCK,
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PSD33XX
AC/DC PARAMETERS These tables describe the AD and DC parameters of the PSD33XX Devices: s DC Electrical Specification
s s
- WRITE Timing - Power-down and RESET Timing The following are issues concerning the parameters presented: s In the DC specification the supply current is given for different modes of operation.
s
AC Timing Specification PLD Timing - Combinatorial Timing - Synchronous Clock Mode - Asynchronous Clock Mode - Input Macrocell Timing
s
MCU Module Timing - READ Timing
s
The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figure 44 and Figure 45 show the PLD mA/MHz as a function of the number of Product Terms (PT) used. In the PLD timing parameters, add the required delay when Turbo Bit is '0.'
Figure 44. PLD ICC /Frequency Consumption (5V range)
110 100 90 80 ICC - (mA) 70
FF O
VCC = 5V
ON RBO
%) (100
TU
60
TU RB
50 40 30 20 10 0 0 5
BO TUR
ON
(25%
)
O
O RB TU
F OF
PT 100% PT 25%
10
15
20
25
AI02894
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
Figure 45. PLD ICC /Frequency Consumption (3V range)
60 VCC = 3V 50 ICC - (mA) 40
BO TUR ON ( 100% )
O FF
30 20 10
TU RB O
TURB
(2 O ON
5%)
TU
0 0
RB
5
O
OF
F
PT 100% PT 25%
10
15
20
25
AI03100
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
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PSD33XX
Table 101. PSD Module Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off)
Conditions MCU Clock Frequency Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode Number of product terms used (from fitter report) % of total product terms Turbo Mode = 45 PT = 45/182 = 24.7% = Off Calculation (using typical values) ICC total = ICC(MCUactive) x %MCUactive + ICC(PSDactive) x %PSDactive + IPD(pwrdown) x %pwrdown ICC(MCUactive) IPD(pwrdown) ICC(PSDactive) = 20mA = 250A = ICC(ac) + ICC(dc) = %flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD) = 0.8 x 2.5 mA/MHz x 2MHz + 0.15 x 1.5 mA/MHz x 2MHz + 24 mA = (4 + 0.45 + 24) mA = 28.45mA ICC total = 20mA x 40% + 28.45mA x 40% + 250A x 60% = 8mA + 11.38mA + 150A = 19.53mA This is the operating power with no Flash memory Erase or Program cycles in progress. Calculation is based on all I/ O pins being disconnected and IOUT = 0 mA. = 40% = 60% = 8MHz = 2MHz = 80% = 15% = 5% (no additional power above base) = 12MHz
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PSD33XX
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 102. Absolute Maximum Ratings
Symbol TSTG TLEAD VIO VCC VPP VESD Storage Temperature Lead Temperature during Soldering (20 seconds max.)(1) Input and Output Voltage (Q = VOH or Hi-Z) Supply Voltage Device Programmer Supply Voltage Electrostatic Discharge Voltage (Human Body Model)(2) -0.5 -0.5 -0.5 -2000 Parameter Min. -65 Max. 125 235 6.5 6.5 14.0 2000 Unit C C V V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 , R2=500 )
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 103. Operating Conditions (5V Devices)
Symbol VCC TA Supply Voltage Ambient Operating Temperature (industrial) Parameter
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Min. 4.5 -40 0
Max. 5.5 85 70
Unit V C C
Ambient Operating Temperature (commercial)
Table 104. Operating Conditions (3.3V Devices)
Symbol VCC TA Ambient Operating Temperature (commercial) 0 70 C Supply Voltage Ambient Operating Temperature (industrial) Parameter Min. 3.0 -40 Max. 3.6 85 Unit V C
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PSD33XX
Table 105. AC Symbols for Timing
Signal Letters A C D I L N P Q R W B M Address Clock Input Data Instruction ALE RESET Input or Output PSEN signal Output Data RD signal WR signal VSTBY Output Output Macrocell t L H V X Z PW Time Logic Level Low or ALE Logic Level High Valid No Longer a Valid Logic Level Float Pulse Width Signal Behavior
Example: tAVLX - Time from Address Valid to ALE Invalid. Figure 46. Switching Waveforms - Key
WAVEFORMS INPUTS OUTPUTS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM HI TO LO MAY CHANGE FROM LO TO HI
WILL BE CHANGING FROM HI TO LO WILL BE CHANGING LO TO HI
DON'T CARE
CHANGING, STATE UNKNOWN
OUTPUTS ONLY
CENTER LINE IS TRI-STATE
AI03102
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PSD33XX
Table 106. Preliminary MCU Module DC Characteristics
Symbol VCC Parameter Supply Voltage(1) High Level Input Voltage (Ports 0, 1, 2, 3, 4, XTAL1, RESET) 5V Tolerant - max voltage 5.5V Low Level Input Voltage (Ports 0, 1, 2, 3, 4, XTAL1, RESET) Output Low Voltage (Port 4) Output Low Voltage (Other Ports) Output High Voltage (Ports 4 push-pull) Output High Voltage (Other Ports push-pull) XTAL Open Bias Voltage (XTAL1, XTAL2) RESET Pin Pull-up Current (RESET) XTAL Feedback Resistor Current (XTAL1) Input High Leakage Current (Port 0) Input High Leakage Current (Port 1, 2, 3, 4) Input Low Leakage Current (Port 1, 2, 3, 4) Power-down Mode Active - 12MHz Idle - 12MHz ICC-CPU (Note 3,4,5) Active - 24MHz Idle - 24MHz Active - 40MHz Idle - 40MHz VLVD
Note: 1. 2. 3.
Test Conditions
Min. 3.0
Typ.
Max. 3.6
Unit V
VIH
3.0V < VCC < 3.6V
0.7VCC
5.5
V
VIL
3.0V < VCC < 3.6V IOL = 10mA
VSS - 0.5
0.3VCC 0.6
V V V
VOL1
VOL2
IOL =5mA
0.6
V V
VOH1
IOH = -10mA
2.4
V V
VOH2 VOP IRST IFR IIHL1 IIHL2 IILL IPD (Note 2)
IOH = -5mA
2.4
V V
IOL = 3.2mA VIN = VSS XTAL1 = VCC; XTAL2 = VSS VSS < VIN < 5.5V VIH = 2.3V VIL < 0.5V VCC = 3.6V LVD Logic disabled LVD Logic enabled VCC = 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.3V
1.0 -10 TBD (-20) -10 -10 -10
2.0 -55 TBD (-50) 10 10 10 10 80 TBD TBD TBD TBD TBD TBD
V A A A A A A A mA mA mA mA mA mA
LVD Low Voltage Detect Reset Threshold
2.3
2.5
2.7
V
Power supply (VCC) is always 3.0 to 3.6V for the MCU Module. VDD for the PSD Module may be 3V or 5V. IPD (Power-down Mode) is measured with: XTAL1 = VSS; XTAL2 = NC; RESET = VCC; Port 0 = VCC; all other pins are disconnected. ICC-CPU (Active Mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V, XTAL2 = NC; RESET = VSS; Port 0 = VCC ; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). 4. ICC-CPU (Idle Mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V, XTAL2 = NC; RESET = VCC; Port 0 = VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). 5. I/O current = 0mA, all I/O pins are disconnected.
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PSD33XX
Table 107. PSD Module DC Characteristics (with 5V VDD)
Symbol VIH VIL VLKO Parameter Input High Voltage Input Low Voltage VDD (min) for Flash Erase and Program IOL = 20A, VDD = 4.5V VOL Output Low Voltage IOL = 8mA, VDD = 4.5V Output High Voltage Except VSTBY On Output High Voltage VSTBY On SRAM Stand-by Voltage SRAM Stand-by Current Idle Current (VSTBY input) SRAM Data Retention Voltage Stand-by Supply Current for Power-down Mode Input Leakage Current Output Leakage Current VDD = 0V VDD > VSTBY Only on VSTBY CSI > VDD - 0.3V (Notes 1,2) VSS < VIN < VDD 0.45 < VOUT < VDD PLD_TURBO = Off, f = 0MHz (Note 4) PLD Only Operating ICC (DC) Supply (Note 4) Current Flash memory PLD_TURBO = On, f = 0MHz During Flash memory WRITE/Erase Only Read only, f = 0MHz SRAM PLD AC Adder ICC (AC) Flash memory AC Adder (Note 4) SRAM AC Adder
Note: 1. 2. 3. 4. CSI deselected or internal Power-down mode is active. PLD is in non-Turbo mode, and none of the inputs are switching. Please see Figure 44 for the PLD current calculation. IOUT = 0 mA
Test Condition (in addition to those in Table 103, page 98) 4.5V < VDD < 5.5V 4.5V < VDD < 5.5V
Min. 2 -0.5 2.5
Typ.
Max. VDD +0.5 0.8 4.2
Unit V V V V V V V V
0.01 0.25 4.4 2.4 VSTBY - 0.8 2.0 0.5 -0.1 2 50 -1 -10 0.1 5 0 400 15 0 0 4.49 3.9
0.1 0.45
VOH VOH1 VSTBY ISTBY IIDLE VDF ISB ILI ILO
IOH = -20A, VDD = 4.5V IOH = -2mA, VDD = 4.5V IOH1 = 1A
VDD 1 0.1 VDD - 0.2 200 1 10
V A A V A A A A/PT
700 30 0 0 Note 3
A/PT mA mA mA
f = 0MHz
2.5 1.5
3.5 3.0
mA/ MHz mA/ MHz
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PSD33XX
Table 108. PSD Module DC Characteristics (with 3.3V VDD)
Symbol VIH VIL VLKO Parameter High Level Input Voltage Low Level Input Voltage VDD (min) for Flash Erase and Program IOL = 20A, VDD = 3.0V VOL Output Low Voltage IOL = 4mA, VDD = 3.0V Output High Voltage Except VSTBY On Output High Voltage VSTBY On SRAM Stand-by Voltage SRAM Stand-by Current Idle Current (VSTBY input) SRAM Data Retention Voltage Stand-by Supply Current for Power-down Mode Input Leakage Current Output Leakage Current VDD = 0V VDD > VSTBY Only on VSTBY CSI > VDD - 0.3V (Notes 1,2) VSS < VIN < VDD 0.45 < VIN < VDD PLD_TURBO = Off, f = 0MHz (Note 2) PLD Only Operating ICC (DC) Supply (Note 4) Current Flash memory PLD_TURBO = On, f = 0MHz During Flash memory WRITE/Erase Only Read only, f = 0MHz SRAM PLD AC Adder ICC (AC) Flash memory AC Adder (Note 4) SRAM AC Adder
Note: 1. 2. 3. 4. CSI deselected or internal PD is active. PLD is in non-Turbo mode, and none of the inputs are switching. Please see Figure 45 for the PLD current calculation. IOUT = 0 mA
Test Condition (in addition to those in Table 104, page 98) 3.0V < VDD < 3.6V 3.0V < VDD < 3.6V
Min. 0.7VDD -0.5 1.5
Typ.
Max. VDD +0.5 0.8 2.2
Unit V V V V V V V V
0.01 0.15 2.9 2.7 VSTBY - 0.8 2.0 0.5 -0.1 2 25 -1 -10 0.1 5 0 200 10 0 0 Note 3 1.5 0.8 2.99 2.8
0.1 0.45
VOH VOH1 VSTBY ISTBY IIDLE VDF ISB ILI ILO
IOH = -20A, VDD = 3.0V IOH = -1mA, VDD = 3.0V IOH1 = 1A
VDD 1 0.1 VDD - 0.2 100 1 10
V A A V A A A A/PT
400 25 0 0
A/PT mA mA mA
f = 0MHz
2.0 1.5
mA/ MHz mA/ MHz
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PSD33XX
Figure 47. External PSEN/READ Cycle (80-pin Device Only)
tLHLL ALE tAVLL PSEN RD tLLAX tAZPL MCU AD0 - AD7 A0-A7 tAVIV MCU A8 - A11 A8-A11 INSTR IN tPXIX A8-A11
AI07875
tLLPL
tPLPH
tPXAV tPXIZ A0-A7
Table 109. External PSEN or READ Cycle AC Characteristics (3V or 5V Device)
Symbol tLHLL tAVLL tLLAX tLLPL tPLPH tPXIX tPHIZ tPXAV tAVIV tAZPL Parameter ALE pulse width Address setup to ALE Address hold after ALE ALE to PSEN or RD PSEN or RD pulse width(2) Input instruction/data hold after PSEN or RD Input instruction/data float after PSEN or RD Address hold after PSEN or RD Address to valid instruction/data in Address float to PSEN or RD
(2)
40MHz Oscillator(1) Min 17 13 7.5 7.5 40 2 10.5 7.5 70 -2 Max
Variable Oscillator 1/tCLCL = 8 to 40MHz Min tCLCL - 8 tCLCL - 12 0.5tCLCL - 5 0.5tCLCL - 5 ntCLCL - 10 2 0.5tCLCL - 2 0.5tCLCL - 5 mtCLCL - 5 -2 Max
Unit ns ns ns ns ns ns ns ns ns ns
Note: 1. BUSCON Register is configured for 4 PFQCLK. 2. Refer to Table 110 for "n" and "m" values.
Table 110. n, m, and x, y Values
# of PFQCLK in BUSCON Reg. 3 4 5 6 7 PSEN (code) Cycle n 1 2 3 4 m 2 3 4 5 n 2 3 4 5 READ Cycle m 3 4 5 6 x 2 3 4 5 WRITE Cycle y 1 2 3 4
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PSD33XX
Figure 48. External WRITE Cycle (80-pin Device Only)
ALE tLHLL PSEN tLLWL WR tWHQX tAVLL tLLAX MCU AD0 - AD7
A0-A7
tWHLH
tWLWH
tQVWH
DATA OUT A0-A7 INSTR IN
tAVWL MCU A8 - A11
A8-A11 A8-A11
AI07877
Table 111. External WRITE Cycle AC Characteristics (3V or 5V Device)
Symbol Parameter 40MHz Oscillator(1) Min tLHLL tAVLL tLLAX tWLWH tLLWL tAVWL tWHLH tQVWH tWHQX ALE pulse width Address Setup to ALE Address hold after ALE WR pulse width(2) ALE to WR Address valid to WR WR High to ALE High Data setup before WR(y) Data hold after WR 17 13 7.5 40 7.5 27.5 6.5 20 6.5 14.5 14.5 Max Variable Oscillator 1/tCLCL = 8 to 40MHz Min tCLCL - 8 tCLCL - 12 0.5tCLCL - 5 xtCLCL - 10 0.5tCLCL - 5 1.5tCLCL - 10 0.5tCLCL - 6 ytCLCL - 5 0.5tCLCL - 6 0.5tCLCL + 2 0.5tCLCL + 2 Max ns ns ns ns ns ns ns ns ns Unit
Note: 1. BUSCON Register is configured for 4 PFQCLK. 2. Refer to Table 110, page 103 for "n" and "m" values.
Table 112. External Clock Drive
Symbol tCLCL tCHCX tCLCX tCLCH tCHCL Parameter(1) Oscillator period High time Low time Rise time Fall time 40MHz Oscillator Min Max Variable Oscillator 1/tCLCL = 8 to 40MHz Min 25 10 10 Max 125 tCLCL - tCLCX tCLCL - tCLCX 10 10 ns ns ns ns ns Unit
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PSD33XX
Table 113. A/D Analog Specification
Symbol Normal IDD Power-down AVIN AVREF(2) Analog Input Voltage Analog Reference Voltage GND Parameter Test Conditions(1) Input = AVREF Min. Typ. 4.0 40 AVREF 3.6 10 Input = 0 - AVREF (V) Input = 0 - AVREF (V) fSAMPLE = 500ksps 50 48 2 8MHz Calibration Time 1 54 52 8 4 16 60 50 54 16 8 1 1 Max. Unit mA A V V bits LSB LSB dB dB MHz S mS kHz dB
Accuracy Resolution INL DNL SNR SNDR ACLK tC tCAL fIN THD Integral Nonlinearity Differential Nonlinearity Signal to Noise Ratio Signal to Noise Distortion Ratio ADC Clock Conversion Time Power-up Time Analog Input Frequency Total Harmonic Distortion
Note: 1. fIN 2kHz, ACLK = 8MHz, AVREF = VCC = 3.3V 2. AVREF = VCC in 52-pin package.
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PSD33XX
Figure 49. Input to Output Disable / Enable
INPUT
tER INPUT TO OUTPUT ENABLE/DISABLE
tEA
AI02863
Table 114. CPLD Combinatorial Timing (5V PSD Module)
Symbol tPD(2) tEA tER tARP tARPW tARD Parameter CPLD Input Pin/Feedback to CPLD Combinatorial Output CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay CPLD Register Clear or Preset Pulse Width CPLD Array Delay Any macrocell 10 11 +2 Conditions Min Max 20 21 21 21 PT Turbo Slew Aloc Off rate(1) +2 + 10 + 10 + 10 + 10 + 10 -2 -2 -2 -2 Unit ns ns ns ns ns ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only)
Table 115. CPLD Combinatorial Timing (3V PSD Module)
Symbol tPD(2) tEA tER tARP tARPW tARD Parameter CPLD Input Pin/Feedback to CPLD Combinatorial Output CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay CPLD Register Clear or Preset Pulse Width CPLD Array Delay Any macrocell 25 25 +4 Conditions Min Max 40 43 43 40 PT Turbo Slew Aloc Off rate(1) +4 + 20 + 20 + 20 + 20 + 20 -6 -6 -6 -6 Unit ns ns ns ns ns ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only)
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PSD33XX
Figure 50. Synchronous Clock Mode Timing - PLD
tCH tCL
CLKIN
tS INPUT
tH
tCO REGISTERED OUTPUT
AI02860
Table 116. CPLD Macrocell Synchronous Clock Mode Timing (5V PSD Module)
Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data tS tH tCH tCL tCO tARD tMIN Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period(2) Clock Input Clock Input Clock Input Any macrocell tCH+tCL 12 Conditions 1/(tS+tCO) 1/(tS+tCO-10) 1/(tCH+tCL) 12 0 6 6 13 11 +2 -2 Min Max 40.0 66.6 83.3 +2 + 10 PT Turbo Slew Aloc Off rate(1) Unit MHz MHz MHz ns ns ns ns ns ns ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL.
Table 117. CPLD Macrocell Synchronous Clock Mode Timing (3V PSD Module)
Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data tS tH tCH tCL tCO tARD tMIN Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period
(2)
Conditions 1/(tS+tCO) 1/(tS+tCO-10) 1/(tCH+tCL)
Min
Max 22.2 28.5 40.0
PT Aloc
Turbo Slew Off rate(1)
Unit MHz MHz MHz
20 0 Clock Input Clock Input Clock Input Any macrocell tCH+tCL 25 15 10 25 25
+4
+ 20
ns ns ns ns -6 ns ns ns
+4
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL.
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PSD33XX
Figure 51. Asynchronous RESET / Preset
tARPW
RESET/PRESET INPUT tARP REGISTER OUTPUT
AI02864
Figure 52. Asynchronous Clock Mode Timing (product term clock)
tCHA tCLA
CLOCK
tSA
tHA
INPUT tCOA REGISTERED OUTPUT
AI02859
Table 118. CPLD Macrocell Asynchronous Clock Mode Timing (5V PSD Module)
Symbol Parameter Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data tSA tHA tCHA tCLA tCOA tARDA tMINA Input Setup Time Input Hold Time Clock Input High Time Clock Input Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Any macrocell 1/fCNTA 16 Conditions 1/(tSA+tCOA) 1/(tSA+tCOA-10) 1/(tCHA+tCLA) 7 8 9 9 21 11 +2 + 10 + 10 + 10 -2 Min Max 38.4 62.5 71.4 +2 + 10 PT Turbo Slew Aloc Off Rate Unit MHz MHz MHz ns ns ns ns ns ns ns
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PSD33XX
Table 119. CPLD Macrocell Asynchronous Clock Mode Timing (3V PSD Module)
Symbol Parameter Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data tSA tHA tCHA tCLA tCOA tARD tMINA Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Any macrocell 1/fCNTA 36 Conditions 1/(tSA+tCOA) 1/(tSA+tCOA-10) 1/(tCHA+tCLA) 10 12 17 13 36 25 +4 + 20 + 20 + 20 -6 Min Max 21.7 27.8 33.3 +4 + 20 PT Turbo Slew Aloc Off Rate Unit MHz MHz MHz ns ns ns ns ns ns ns
Figure 53. Input Macrocell Timing (Product Term Clock)
t INH
PT CLOCK
t INL
t IS
INPUT
t IH
OUTPUT
t INO
AI03101
Table 120. Input Macrocell Timing (5V PSD Module)
Symbol tIS tIH tINH tINL tINO Parameter Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial Delay Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Min 0 15 9 9 34 +2 + 10 + 10 Max PT Aloc Turbo Off Unit ns ns ns ns ns
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX.
109/123
PSD33XX
Table 121. Input Macrocell Timing (3V PSD Module)
Symbol tIS tIH tINH tINL tINO Parameter Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial Delay Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Min 0 25 12 12 46 +4 + 20 + 20 Max PT Aloc Turbo Off Unit ns ns ns ns ns
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX.
Table 122. Program, WRITE and Erase Times (5V, 3V PSD Modules)
Symbol Flash Program Flash Bulk Erase(1) (pre-programmed) Parameter Min. Typ. 8.5 3 5 1 2.2 14 100,000 100 30 150 30 30 Max. Unit s s s s s s cycles s ns
Flash Bulk Erase (not pre-programmed) tWHQV3 tWHQV2 tWHQV1 Sector Erase (pre-programmed) Sector Erase (not pre-programmed) Byte Program Program / Erase Cycles (per Sector) tWHWLO tQ7VQV Sector Erase Time-Out DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)(2)
Note: 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
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Figure 54. Peripheral I/O READ Timing
ALE
A/D BUS
ADDRESS
DATA VALID
tAVQV ( PA) tSLQV ( PA) CSI tRLQV (PA) RD
tRHQZ (PA)
tDVQV (PA) DATA ON PORT A
AI06610
Table 123. Port A Peripheral Data Mode READ Timing (5V PSD Module)
Symbol tAVQV-PA tSLQV-PA tRLQV-PA tDVQV-PA tRHQZ-PA Parameter Address Valid to Data Valid CSI Valid to Data Valid RD to Data Valid Data In to Data Out Valid RD to Data High-Z (Note 2) Conditions (Note 1) Min Max 37 27 32 22 23 Turbo Off + 10 + 10 Unit ns ns ns ns ns
Note: 1. Any input used to select Port A Data Peripheral Mode. 2. Data is already stable on Port A.
Table 124. Port A Peripheral Data Mode READ Timing (3V PSD Module)
Symbol tAVQV-PA tSLQV-PA tRLQV-PA tDVQV-PA tRHQZ-PA Parameter Address Valid to Data Valid CSI Valid to Data Valid RD to Data Valid Data In to Data Out Valid RD to Data High-Z (Note 2) Conditions (Note 1) Min Max 50 37 45 38 36 Turbo Off + 20 + 20 Unit ns ns ns ns ns
Note: 1. Any input used to select Port A Data Peripheral Mode. 2. Data is already stable on Port A.
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Figure 55. Peripheral I/O WRITE Timing
ALE
A / D BUS
ADDRESS
DATA OUT
tWLQV WR
(PA)
tWHQZ (PA)
tDVQV (PA) PORT A DATA OUT
AI06611
Table 125. Port A Peripheral Data Mode WRITE Timing (5V PSD Module)
Symbol tWLQV-PA tDVQV-PA tWHQZ-PA Parameter WR to Data Propagation Delay Data to Port A Data Propagation Delay WR Invalid to Port A Tri-state (Note 1) Conditions Min Max 25 22 20 Unit ns ns ns
Note: 1. Data stable on Port 0 pins to data on Port A.
Table 126. Port A Peripheral Data Mode WRITE Timing (3V PSD Module)
Symbol tWLQV-PA tDVQV-PA tWHQZ-PA Parameter WR to Data Propagation Delay Data to Port A Data Propagation Delay WR Invalid to Port A Tri-state (Note 1) Conditions Min Max 42 38 33 Unit ns ns ns
Note: 1. Data stable on Port 0 pins to data on Port A.
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Figure 56. Reset (RESET) Timing
VCC
VCC(min) tNLNH tNLNH-A Warm Reset
tNLNH-PO Power-On Reset
RESET
AI07874
Table 127. Reset (RESET) Timing (5V PSD Module)
Symbol tNLNH tNLNH-PO tNLNH-A tOPR Parameter RESET Active Low Time(1) Power-on Reset Active Low Time Warm RESET (2) RESET High to Operational Device Conditions Min 150 1 25 120 Max Unit ns ms s ns
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 128. Reset (RESET) Timing (3V PSD Module)
Symbol tNLNH tNLNH-PO tNLNH-A tOPR Parameter RESET Active Low Time(1) Power-on Reset Active Low Time Warm RESET (2) RESET High to Operational Device Conditions Min 300 1 25 300 Max Unit ns ms s ns
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 129. VSTBYON Definitions Timing (5V, 3V PSD Modules)
Symbol tBVBH tBXBL Parameter VSTBY Detection to VSTBYON Output High VSTBY Off Detection to VSTBYON Output Low Conditions (Note 1) (Note 1) Min Typ 20 20 Max Unit s s
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.
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Figure 57. ISC Timing
t ISCCH
TCK
t ISCCL t ISCPSU t ISCPH
TDI/TMS
t ISCPZV t ISCPCO
ISC OUTPUTS/TDO
t ISCPVZ
ISC OUTPUTS/TDO
AI02865
Table 130. ISC Timing (5V PSD Module)
Symbol tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH tISCPCO tISCPZV tISCPVZ Parameter Clock (TCK, PC1) Frequency (except for PLD) Clock (TCK, PC1) High Time (except for PLD) Clock (TCK, PC1) Low Time (except for PLD) Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Low Time (PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance Conditions (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) 240 240 7 5 21 21 21 23 23 2 Min Max 20 Unit MHz ns ns MHz ns ns ns ns ns ns ns
Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode. 2. For Program or Erase PLD only.
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Table 131. ISC Timing (3V PSD Module)
Symbol tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH tISCPCO tISCPZV tISCPVZ Parameter Clock (TCK, PC1) Frequency (except for PLD) Clock (TCK, PC1) High Time (except for PLD) Clock (TCK, PC1) Low Time (except for PLD) Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Low Time (PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance Conditions (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) 240 240 12 5 30 30 30 40 40 2 Min Max 12 Unit MHz ns ns MHz ns ns ns ns ns ns ns
Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode. 2. For Program or Erase PLD only.
Figure 58. MCU Module AC Measurement I/O Waveform
VCC - 0.5V
0.2 VCC + 0.9V Test Points 0.2 VCC - 0.1V
AI06650
0.45V
Note: AC inputs during testing are driven at VCC-0.5V for a logic '1,' and 0.45V for a logic '0.' Timing measurements are made at VIH(min) for a logic '1,' and VIL(max) for a logic '0'
Figure 59. PSD Module AC Float I/O Waveform
VOH - 0.1V Test Reference Points VLOAD - 0.1V 0.2 VCC - 0.1V VOL + 0.1V
AI06651
VLOAD + 0.1V
Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH or VOL level occurs IOL and IOH 20mA
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Figure 60. External Clock Cycle
Figure 61. Recommended Oscillator Circuits
Note: C1, C2 = 30pF 10pF for crystals For ceramic resonators, contact resonator manufacturer Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
Figure 62. PSD Module AC Measurement I/O Waveform
Figure 63. PSD Module AC Measurement Load Circuit
2.01 V
3.0V Test Point 0V
AI03103b
195 1.5V Device Under Test
CL = 30 pF (Including Scope and Jig Capacitance)
AI03104b
Table 132. I/O Pin Capacitance
Symbol CIN COUT Parameter Input Capacitance (for input pins) Output Capacitance (for input/ output pins) Test Condition VIN = 0V VOUT = 0V Typ.2 4 8 Max. 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. Typical values are for TA = 25C and nominal supply voltages.
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PART NUMBERING Table 133. Ordering Information Scheme
Example: Device Type PSD = Microcontroller PSD Family 32 = 8032 core 33 = Turbo core SRAM Size 1 = 16Kbit 3 = 64Kbit 5 = 256Kbit Main Flash Memory Size 2 = 512Kbit 3 = 1Mbit 4 = 2Mbit IP Mix D = IP Mix: I2C, SPI, UART (2), IrDA, ADC, Supervisor, PCA Operating Voltage blank = VCC = 4.5 to 5.5V V = VCC = 3.0 to 3.6V Speed -24 = 24MHz -40 = 40MHz Package T = 52-pin TQFP U = 80-pin TQFP Temperature Range 1 = 0 to 70C 6 = -40 to 85C Shipping Option Tape & Reel Packing = T PSD 33 3 4 D V - 24 U 6 T
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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PACKAGE MECHANICAL INFORMATION Figure 64. TQFP52 - 52-lead Plastic Quad Flatpack Package Outline
D D1 D2 A2
e Ne E2 E1 E b
N 1
Nd L1
A CP
c
QFP-A
Note: Drawing is not to scale.
A1
L
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Table 134. TQFP52 - 52-lead Plastic Quad Flatpack Package Mechanical Data
mm Symb Typ A A1 A2 b c D D1 D2 E E1 E2 e L L1 n Nd Ne CP - 12.00 10.00 7.80 0.65 - 1.00 - - 0.45 - 0 52 13 13 - 0.10 - - 0.75 - 7 - - - - 0.473 0.394 0.307 0.026 - 0.039 - - 0.018 - 0 52 13 13 - 0.004 - 0.030 - 7 - - - - - - - - - 12.00 10.00 Min - 0.05 1.25 0.20 0.07 - - Max 1.75 0.20 1.55 0.40 0.23 - - Typ - - - - - 0.473 0.394 Min - 0.002 0.049 0.008 0.002 - - Max 0.069 0.008 0.061 0.016 0.009 - - inches
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Figure 65. TQFP80 - 80-lead Plastic Quad Flatpack Package Outline
D D1 D2 A2
e Ne E2 E1 E b
N 1
Nd L1
A CP
c
QFP-A
Note: Drawing is not to scale.
A1
L
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Table 135. TQFP80 - 80-lead Plastic Quad Flatpack Package Mechanical Data
mm Symb Typ A A1 A2 b c D D1 D2 E E1 E2 e L L1 n Nd Ne CP - - - 1.40 0.22 - 14.00 12.00 9.50 14.00 12.00 9.50 0.50 0.60 1.00 3.5 Min - 0.05 1.35 0.17 0.09 - - - - - - - 0.45 - 0 80 20 20 - 0.08 - Max 1.60 0.15 1.45 0.27 0.20 - - - - - - - 0.75 - 7 Typ - - 0.055 0.009 - 0.551 0.472 0.374 0.473 0.394 0.374 0.020 0.024 0.039 3.5 Min - 0.002 0.053 0.007 0.004 - - - - - - - 0.018 - 0 80 20 20 - 0.003 Max 0.063 0.006 0.057 0.011 0.008 - - - - - - - 0.030 - 7 inches
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REVISION HISTORY Table 136. Document Revision History
Date July 2003 Rev. # 1.0 First Issue Revision Details
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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